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vladimirradosavljevicvladimirradosavljevic
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[MCP] Optimize copies when src is used during backward propagation (llvm#111130)
Before this patch, redundant COPY couldn't be removed for the following case: ``` $R0 = OP ... ... // Read of %R0 $R1 = COPY killed $R0 ``` This patch adds support for tracking the users of the source register during backward propagation, so that we can remove the redundant COPY in the above case and optimize it to: ``` $R1 = OP ... ... // Replace all uses of %R0 with $R1 ```
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‎llvm/lib/CodeGen/MachineCopyPropagation.cpp‎

Lines changed: 77 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -110,6 +110,7 @@ class CopyTracker {
110110
struct CopyInfo {
111111
MachineInstr *MI = nullptr;
112112
MachineInstr *LastSeenUseInCopy = nullptr;
113+
SmallPtrSet<MachineInstr *, 4> SrcUsers;
113114
SmallVector<MCRegister, 4> DefRegs;
114115
bool Avail = false;
115116
};
@@ -224,6 +225,43 @@ class CopyTracker {
224225
}
225226
}
226227

228+
/// Track copy's src users, and return false if that can't be done.
229+
/// We can only track if we have a COPY instruction which source is
230+
/// the same as the Reg.
231+
bool trackSrcUsers(MCRegister Reg, MachineInstr &MI,
232+
const TargetRegisterInfo &TRI, const TargetInstrInfo &TII,
233+
bool UseCopyInstr) {
234+
MCRegUnit RU = *TRI.regunits(Reg).begin();
235+
MachineInstr *AvailCopy = findCopyDefViaUnit(RU, TRI);
236+
if (!AvailCopy)
237+
return false;
238+
239+
std::optional<DestSourcePair> CopyOperands =
240+
isCopyInstr(*AvailCopy, TII, UseCopyInstr);
241+
Register Src = CopyOperands->Source->getReg();
242+
243+
// Bail out, if the source of the copy is not the same as the Reg.
244+
if (Src != Reg)
245+
return false;
246+
247+
auto I = Copies.find(RU);
248+
if (I == Copies.end())
249+
return false;
250+
251+
I->second.SrcUsers.insert(&MI);
252+
return true;
253+
}
254+
255+
/// Return the users for a given register.
256+
SmallPtrSet<MachineInstr *, 4> getSrcUsers(MCRegister Reg,
257+
const TargetRegisterInfo &TRI) {
258+
MCRegUnit RU = *TRI.regunits(Reg).begin();
259+
auto I = Copies.find(RU);
260+
if (I == Copies.end())
261+
return {};
262+
return I->second.SrcUsers;
263+
}
264+
227265
/// Add this copy's registers into the tracker's copy maps.
228266
void trackCopy(MachineInstr *MI, const TargetRegisterInfo &TRI,
229267
const TargetInstrInfo &TII, bool UseCopyInstr) {
@@ -236,7 +274,7 @@ class CopyTracker {
236274

237275
// Remember Def is defined by the copy.
238276
for (MCRegUnit Unit : TRI.regunits(Def))
239-
Copies[Unit] = {MI, nullptr, {}, true};
277+
Copies[Unit] = {MI, nullptr, {}, {}, true};
240278

241279
// Remember source that's copied to Def. Once it's clobbered, then
242280
// it's no longer available for copy propagation.
@@ -427,6 +465,8 @@ class MachineCopyPropagation : public MachineFunctionPass {
427465
bool hasImplicitOverlap(const MachineInstr &MI, const MachineOperand &Use);
428466
bool hasOverlappingMultipleDef(const MachineInstr &MI,
429467
const MachineOperand &MODef, Register Def);
468+
bool canUpdateSrcUsers(const MachineInstr &Copy,
469+
const MachineOperand &CopySrc);
430470

431471
/// Candidates for deletion.
432472
SmallSetVector<MachineInstr *, 8> MaybeDeadCopies;
@@ -667,6 +707,27 @@ bool MachineCopyPropagation::hasOverlappingMultipleDef(
667707
return false;
668708
}
669709

710+
/// Return true if it is safe to update all users of the \p CopySrc register
711+
/// in the given \p Copy instruction.
712+
bool MachineCopyPropagation::canUpdateSrcUsers(const MachineInstr &Copy,
713+
const MachineOperand &CopySrc) {
714+
assert(CopySrc.isReg() && "Expected a register operand");
715+
for (auto *SrcUser : Tracker.getSrcUsers(CopySrc.getReg(), *TRI)) {
716+
if (hasImplicitOverlap(*SrcUser, CopySrc))
717+
return false;
718+
719+
for (MachineOperand &MO : SrcUser->uses()) {
720+
if (!MO.isReg() || !MO.isUse() || MO.getReg() != CopySrc.getReg())
721+
continue;
722+
if (MO.isTied() || !MO.isRenamable() ||
723+
!isBackwardPropagatableRegClassCopy(Copy, *SrcUser,
724+
MO.getOperandNo()))
725+
return false;
726+
}
727+
}
728+
return true;
729+
}
730+
670731
/// Look for available copies whose destination register is used by \p MI and
671732
/// replace the use in \p MI with the copy's source register.
672733
void MachineCopyPropagation::forwardUses(MachineInstr &MI) {
@@ -1033,13 +1094,25 @@ void MachineCopyPropagation::propagateDefs(MachineInstr &MI) {
10331094
if (hasOverlappingMultipleDef(MI, MODef, Def))
10341095
continue;
10351096

1097+
if (!canUpdateSrcUsers(*Copy, *CopyOperands->Source))
1098+
continue;
1099+
10361100
LLVM_DEBUG(dbgs() << "MCP: Replacing " << printReg(MODef.getReg(), TRI)
10371101
<< "\n with " << printReg(Def, TRI) << "\n in "
10381102
<< MI << " from " << *Copy);
10391103

10401104
MODef.setReg(Def);
10411105
MODef.setIsRenamable(CopyOperands->Destination->isRenamable());
10421106

1107+
for (auto *SrcUser : Tracker.getSrcUsers(Src, *TRI)) {
1108+
for (MachineOperand &MO : SrcUser->uses()) {
1109+
if (!MO.isReg() || !MO.isUse() || MO.getReg() != Src)
1110+
continue;
1111+
MO.setReg(Def);
1112+
MO.setIsRenamable(CopyOperands->Destination->isRenamable());
1113+
}
1114+
}
1115+
10431116
LLVM_DEBUG(dbgs() << "MCP: After replacement: " << MI << "\n");
10441117
MaybeDeadCopies.insert(Copy);
10451118
Changed = true;
@@ -1105,7 +1178,9 @@ void MachineCopyPropagation::BackwardCopyPropagateBlock(
11051178
CopyDbgUsers[Copy].insert(&MI);
11061179
}
11071180
}
1108-
} else {
1181+
} else if (!Tracker.trackSrcUsers(MO.getReg().asMCReg(), MI, *TRI, *TII,
1182+
UseCopyInstr)) {
1183+
// If we can't track the source users, invalidate the register.
11091184
Tracker.invalidateRegister(MO.getReg().asMCReg(), *TRI, *TII,
11101185
UseCopyInstr);
11111186
}

‎llvm/test/CodeGen/AArch64/machine-cp-backward-uses.mir‎

Lines changed: 58 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,58 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py UTC_ARGS: --version 5
2+
# RUN: llc -mtriple=aarch64-none-linux-gnu -run-pass machine-cp -verify-machineinstrs -o - %s | FileCheck %s
3+
4+
# Normal case
5+
---
6+
name: test1
7+
body: |
8+
bb.0:
9+
liveins: $w2
10+
; CHECK-LABEL: name: test1
11+
; CHECK: liveins: $w2
12+
; CHECK-NEXT: {{ $}}
13+
; CHECK-NEXT: renamable $w0 = MOVi32imm 5
14+
; CHECK-NEXT: renamable $w3 = ADDWrr renamable $w0, killed renamable $w2
15+
; CHECK-NEXT: RET_ReallyLR implicit killed $w0
16+
renamable $w1 = MOVi32imm 5
17+
renamable $w3 = ADDWrr renamable $w1, killed renamable $w2
18+
renamable $w0 = COPY killed renamable $w1
19+
RET_ReallyLR implicit killed $w0
20+
...
21+
22+
# Not renamable use
23+
---
24+
name: test2
25+
body: |
26+
bb.0:
27+
liveins: $w2
28+
; CHECK-LABEL: name: test2
29+
; CHECK: liveins: $w2
30+
; CHECK-NEXT: {{ $}}
31+
; CHECK-NEXT: renamable $w1 = MOVi32imm 5
32+
; CHECK-NEXT: renamable $w3 = ADDWrr $w1, killed renamable $w2
33+
; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
34+
; CHECK-NEXT: RET_ReallyLR implicit killed $w0
35+
renamable $w1 = MOVi32imm 5
36+
renamable $w3 = ADDWrr $w1, killed renamable $w2
37+
renamable $w0 = COPY killed renamable $w1
38+
RET_ReallyLR implicit killed $w0
39+
...
40+
41+
# Implicit use
42+
---
43+
name: test3
44+
body: |
45+
bb.0:
46+
liveins: $w2
47+
; CHECK-LABEL: name: test3
48+
; CHECK: liveins: $w2
49+
; CHECK-NEXT: {{ $}}
50+
; CHECK-NEXT: renamable $w1 = MOVi32imm 5
51+
; CHECK-NEXT: renamable $w3 = ADDWrr renamable $w1, killed renamable $w2, implicit $w1
52+
; CHECK-NEXT: renamable $w0 = COPY killed renamable $w1
53+
; CHECK-NEXT: RET_ReallyLR implicit killed $w0
54+
renamable $w1 = MOVi32imm 5
55+
renamable $w3 = ADDWrr renamable $w1, killed renamable $w2, implicit $w1
56+
renamable $w0 = COPY killed renamable $w1
57+
RET_ReallyLR implicit killed $w0
58+
...

‎llvm/test/CodeGen/ARM/umulo-128-legalisation-lowering.ll‎

Lines changed: 2 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,12 +7,11 @@ define { i128, i8 } @muloti_test(i128 %l, i128 %r) unnamed_addr #0 {
77
; ARMV6: @ %bb.0: @ %start
88
; ARMV6-NEXT: push {r4, r5, r6, r7, r8, r9, r10, r11, lr}
99
; ARMV6-NEXT: sub sp, sp, #28
10-
; ARMV6-NEXT: ldr r7, [sp, #72]
10+
; ARMV6-NEXT: ldr lr, [sp, #72]
1111
; ARMV6-NEXT: mov r6, r0
1212
; ARMV6-NEXT: str r0, [sp, #8] @ 4-byte Spill
1313
; ARMV6-NEXT: ldr r4, [sp, #84]
14-
; ARMV6-NEXT: umull r1, r0, r2, r7
15-
; ARMV6-NEXT: mov lr, r7
14+
; ARMV6-NEXT: umull r1, r0, r2, lr
1615
; ARMV6-NEXT: umull r5, r10, r4, r2
1716
; ARMV6-NEXT: str r1, [r6]
1817
; ARMV6-NEXT: ldr r6, [sp, #80]

‎llvm/test/CodeGen/Mips/llvm-ir/sdiv.ll‎

Lines changed: 30 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -388,9 +388,8 @@ define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
388388
; MMR3-NEXT: .cfi_def_cfa_offset 24
389389
; MMR3-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
390390
; MMR3-NEXT: .cfi_offset 31, -4
391-
; MMR3-NEXT: addu $2, $2, $25
392-
; MMR3-NEXT: lw $25, %call16(__divdi3)($2)
393-
; MMR3-NEXT: move $gp, $2
391+
; MMR3-NEXT: addu $gp, $2, $25
392+
; MMR3-NEXT: lw $25, %call16(__divdi3)($gp)
394393
; MMR3-NEXT: jalr $25
395394
; MMR3-NEXT: nop
396395
; MMR3-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
@@ -405,9 +404,8 @@ define signext i64 @sdiv_i64(i64 signext %a, i64 signext %b) {
405404
; MMR6-NEXT: .cfi_def_cfa_offset 24
406405
; MMR6-NEXT: sw $ra, 20($sp) # 4-byte Folded Spill
407406
; MMR6-NEXT: .cfi_offset 31, -4
408-
; MMR6-NEXT: addu $2, $2, $25
409-
; MMR6-NEXT: lw $25, %call16(__divdi3)($2)
410-
; MMR6-NEXT: move $gp, $2
407+
; MMR6-NEXT: addu $gp, $2, $25
408+
; MMR6-NEXT: lw $25, %call16(__divdi3)($gp)
411409
; MMR6-NEXT: jalr $25
412410
; MMR6-NEXT: lw $ra, 20($sp) # 4-byte Folded Reload
413411
; MMR6-NEXT: addiu $sp, $sp, 24
@@ -549,65 +547,59 @@ define signext i128 @sdiv_i128(i128 signext %a, i128 signext %b) {
549547
; MMR3: # %bb.0: # %entry
550548
; MMR3-NEXT: lui $2, %hi(_gp_disp)
551549
; MMR3-NEXT: addiu $2, $2, %lo(_gp_disp)
552-
; MMR3-NEXT: addiusp -48
553-
; MMR3-NEXT: .cfi_def_cfa_offset 48
554-
; MMR3-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
555-
; MMR3-NEXT: swp $16, 36($sp)
550+
; MMR3-NEXT: addiusp -40
551+
; MMR3-NEXT: .cfi_def_cfa_offset 40
552+
; MMR3-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
553+
; MMR3-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
556554
; MMR3-NEXT: .cfi_offset 31, -4
557555
; MMR3-NEXT: .cfi_offset 17, -8
558-
; MMR3-NEXT: .cfi_offset 16, -12
559-
; MMR3-NEXT: addu $16, $2, $25
556+
; MMR3-NEXT: addu $gp, $2, $25
560557
; MMR3-NEXT: move $1, $7
561-
; MMR3-NEXT: lw $7, 68($sp)
562-
; MMR3-NEXT: lw $17, 72($sp)
563-
; MMR3-NEXT: lw $3, 76($sp)
558+
; MMR3-NEXT: lw $7, 60($sp)
559+
; MMR3-NEXT: lw $17, 64($sp)
560+
; MMR3-NEXT: lw $3, 68($sp)
564561
; MMR3-NEXT: move $2, $sp
565562
; MMR3-NEXT: sw16 $3, 28($2)
566563
; MMR3-NEXT: sw16 $17, 24($2)
567564
; MMR3-NEXT: sw16 $7, 20($2)
568-
; MMR3-NEXT: lw $3, 64($sp)
565+
; MMR3-NEXT: lw $3, 56($sp)
569566
; MMR3-NEXT: sw16 $3, 16($2)
570-
; MMR3-NEXT: lw $25, %call16(__divti3)($16)
567+
; MMR3-NEXT: lw $25, %call16(__divti3)($gp)
571568
; MMR3-NEXT: move $7, $1
572-
; MMR3-NEXT: move $gp, $16
573569
; MMR3-NEXT: jalr $25
574570
; MMR3-NEXT: nop
575-
; MMR3-NEXT: lwp $16, 36($sp)
576-
; MMR3-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
577-
; MMR3-NEXT: addiusp 48
571+
; MMR3-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
572+
; MMR3-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
573+
; MMR3-NEXT: addiusp 40
578574
; MMR3-NEXT: jrc $ra
579575
;
580576
; MMR6-LABEL: sdiv_i128:
581577
; MMR6: # %bb.0: # %entry
582578
; MMR6-NEXT: lui $2, %hi(_gp_disp)
583579
; MMR6-NEXT: addiu $2, $2, %lo(_gp_disp)
584-
; MMR6-NEXT: addiu $sp, $sp, -48
585-
; MMR6-NEXT: .cfi_def_cfa_offset 48
586-
; MMR6-NEXT: sw $ra, 44($sp) # 4-byte Folded Spill
587-
; MMR6-NEXT: sw $17, 40($sp) # 4-byte Folded Spill
588-
; MMR6-NEXT: sw $16, 36($sp) # 4-byte Folded Spill
580+
; MMR6-NEXT: addiu $sp, $sp, -40
581+
; MMR6-NEXT: .cfi_def_cfa_offset 40
582+
; MMR6-NEXT: sw $ra, 36($sp) # 4-byte Folded Spill
583+
; MMR6-NEXT: sw $17, 32($sp) # 4-byte Folded Spill
589584
; MMR6-NEXT: .cfi_offset 31, -4
590585
; MMR6-NEXT: .cfi_offset 17, -8
591-
; MMR6-NEXT: .cfi_offset 16, -12
592-
; MMR6-NEXT: addu $16, $2, $25
586+
; MMR6-NEXT: addu $gp, $2, $25
593587
; MMR6-NEXT: move $1, $7
594-
; MMR6-NEXT: lw $7, 68($sp)
595-
; MMR6-NEXT: lw $17, 72($sp)
596-
; MMR6-NEXT: lw $3, 76($sp)
588+
; MMR6-NEXT: lw $7, 60($sp)
589+
; MMR6-NEXT: lw $17, 64($sp)
590+
; MMR6-NEXT: lw $3, 68($sp)
597591
; MMR6-NEXT: move $2, $sp
598592
; MMR6-NEXT: sw16 $3, 28($2)
599593
; MMR6-NEXT: sw16 $17, 24($2)
600594
; MMR6-NEXT: sw16 $7, 20($2)
601-
; MMR6-NEXT: lw $3, 64($sp)
595+
; MMR6-NEXT: lw $3, 56($sp)
602596
; MMR6-NEXT: sw16 $3, 16($2)
603-
; MMR6-NEXT: lw $25, %call16(__divti3)($16)
597+
; MMR6-NEXT: lw $25, %call16(__divti3)($gp)
604598
; MMR6-NEXT: move $7, $1
605-
; MMR6-NEXT: move $gp, $16
606599
; MMR6-NEXT: jalr $25
607-
; MMR6-NEXT: lw $16, 36($sp) # 4-byte Folded Reload
608-
; MMR6-NEXT: lw $17, 40($sp) # 4-byte Folded Reload
609-
; MMR6-NEXT: lw $ra, 44($sp) # 4-byte Folded Reload
610-
; MMR6-NEXT: addiu $sp, $sp, 48
600+
; MMR6-NEXT: lw $17, 32($sp) # 4-byte Folded Reload
601+
; MMR6-NEXT: lw $ra, 36($sp) # 4-byte Folded Reload
602+
; MMR6-NEXT: addiu $sp, $sp, 40
611603
; MMR6-NEXT: jrc $ra
612604
entry:
613605
%r = sdiv i128 %a, %b

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