Skip to content

Commit c50255c

Browse files
dstogovdstogov
committed
Update IR
IR commit: 682cc0ca6761164dbcd791e5f56283f8e88537d2 Fixes phpGH-13286
1 parent a135517 commit c50255c

File tree

6 files changed

+391
-270
lines changed

6 files changed

+391
-270
lines changed

‎ext/opcache/jit/ir/ir.c‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1299,7 +1299,7 @@ static uint32_t ir_hashtab_hash_size(uint32_t size)
12991299
size |= (size >> 4);
13001300
size |= (size >> 8);
13011301
size |= (size >> 16);
1302-
return size + 1;
1302+
return IR_MAX(size + 1, 4);
13031303
}
13041304

13051305
static void ir_hashtab_resize(ir_hashtab *tab)

‎ext/opcache/jit/ir/ir_aarch64.dasc‎

Lines changed: 26 additions & 26 deletions
Original file line numberDiff line numberDiff line change
@@ -1038,21 +1038,27 @@ static int32_t ir_ref_spill_slot_offset(ir_ctx *ctx, ir_ref ref, ir_reg *reg)
10381038
return IR_SPILL_POS_TO_OFFSET(offset);
10391039
}
10401040

1041-
static ir_mem ir_ref_spill_slot(ir_ctx *ctx, ir_ref ref)
1041+
static ir_mem ir_vreg_spill_slot(ir_ctx *ctx, ir_ref v)
10421042
{
1043-
ir_reg reg;
10441043
int32_t offset;
1044+
ir_reg base;
10451045

1046-
IR_ASSERT(ref >= 0);
1047-
offset = ctx->live_intervals[ctx->vregs[ref]]->stack_spill_pos;
1046+
IR_ASSERT(v > 0 && v <= ctx->vregs_count && ctx->live_intervals[v]);
1047+
offset = ctx->live_intervals[v]->stack_spill_pos;
10481048
IR_ASSERT(offset != -1);
1049-
if (ctx->live_intervals[ctx->vregs[ref]]->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
1049+
if (ctx->live_intervals[v]->flags & IR_LIVE_INTERVAL_SPILL_SPECIAL) {
10501050
IR_ASSERT(ctx->spill_base != IR_REG_NONE);
1051-
reg = ctx->spill_base;
1052-
return IR_MEM_BO(reg, offset);
1051+
return IR_MEM_BO(ctx->spill_base, offset);
10531052
}
1054-
reg = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1055-
return IR_MEM_BO(reg, IR_SPILL_POS_TO_OFFSET(offset));
1053+
base = (ctx->flags & IR_USE_FRAME_POINTER) ? IR_REG_FRAME_POINTER : IR_REG_STACK_POINTER;
1054+
offset = IR_SPILL_POS_TO_OFFSET(offset);
1055+
return IR_MEM_BO(base, offset);
1056+
}
1057+
1058+
static ir_mem ir_ref_spill_slot(ir_ctx *ctx, ir_ref ref)
1059+
{
1060+
IR_ASSERT(!IR_IS_CONST_REF(ref));
1061+
return ir_vreg_spill_slot(ctx, ctx->vregs[ref]);
10561062
}
10571063

10581064
static bool ir_is_same_spill_slot(ir_ctx *ctx, ir_ref ref, ir_mem mem)
@@ -1404,19 +1410,21 @@ static void ir_emit_store_mem_fp(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg r
14041410
}
14051411
}
14061412

1407-
static void ir_emit_store(ir_ctx *ctx, ir_type type, ir_ref dst, ir_reg reg)
1413+
static void ir_emit_store_mem(ir_ctx *ctx, ir_type type, ir_mem mem, ir_reg reg)
14081414
{
1409-
ir_mem mem;
1410-
1411-
IR_ASSERT(dst >= 0);
1412-
mem = ir_ref_spill_slot(ctx, dst);
14131415
if (IR_IS_TYPE_INT(type)) {
14141416
ir_emit_store_mem_int(ctx, type, mem, reg);
14151417
} else {
14161418
ir_emit_store_mem_fp(ctx, type, mem, reg);
14171419
}
14181420
}
14191421

1422+
static void ir_emit_store(ir_ctx *ctx, ir_type type, ir_ref dst, ir_reg reg)
1423+
{
1424+
IR_ASSERT(dst >= 0);
1425+
ir_emit_store_mem(ctx, type, ir_ref_spill_slot(ctx, dst), reg);
1426+
}
1427+
14201428
static void ir_emit_mov(ir_ctx *ctx, ir_type type, ir_reg dst, ir_reg src)
14211429
{
14221430
ir_backend_data *data = ctx->data;
@@ -3558,11 +3566,7 @@ static void ir_emit_vstore(ir_ctx *ctx, ir_ref ref, ir_insn *insn)
35583566
ir_emit_load(ctx, type, op3_reg, insn->op3);
35593567
}
35603568
mem = IR_MEM_BO(fp, offset);
3561-
if (IR_IS_TYPE_INT(type)) {
3562-
ir_emit_store_mem_int(ctx, type, mem, op3_reg);
3563-
} else {
3564-
ir_emit_store_mem_fp(ctx, type, mem, op3_reg);
3565-
}
3569+
ir_emit_store_mem(ctx, type, mem, op3_reg);
35663570
}
35673571

35683572
static ir_mem ir_fuse_addr(ir_ctx *ctx, ir_ref root, ir_ref ref)
@@ -3944,7 +3948,7 @@ static void ir_emit_va_start(ir_ctx *ctx, ir_ref def, ir_insn *insn)
39443948
if (op2_reg != IR_REG_NONE) {
39453949
| str Rx(tmp_reg), [Rx(op2_reg)]
39463950
} else {
3947-
int32_t offset = ir_ref_spill_slot(ctx, insn->op2, &op2_reg);
3951+
int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op2, &op2_reg);
39483952

39493953
| str Rx(tmp_reg), [Rx(op2_reg), #offset]
39503954
}
@@ -4033,7 +4037,7 @@ static void ir_emit_va_arg(ir_ctx *ctx, ir_ref def, ir_insn *insn)
40334037
if (op2_reg != IR_REG_NONE) {
40344038
| str Rx(tmp_reg), [Rx(op2_reg)]
40354039
} else {
4036-
int32_t offset = ir_ref_spill_slot(ctx, insn->op2, &op2_reg);
4040+
int32_t offset = ir_ref_spill_slot_offset(ctx, insn->op2, &op2_reg);
40374041

40384042
| str Rx(tmp_reg), [Rx(op2_reg), #offset]
40394043
}
@@ -4404,11 +4408,7 @@ static int32_t ir_emit_arguments(ir_ctx *ctx, ir_ref def, ir_insn *insn, ir_reg
44044408
} else {
44054409
/* Pass register arguments to stack (REG->MEM moves) */
44064410
if (!IR_IS_CONST_REF(arg) && src_reg != IR_REG_NONE && !IR_REG_SPILLED(src_reg)) {
4407-
if (IR_IS_TYPE_INT(type)) {
4408-
ir_emit_store_mem_int(ctx, type, IR_MEM_BO(IR_REG_STACK_POINTER, stack_offset), src_reg);
4409-
} else {
4410-
ir_emit_store_mem_fp(ctx, type, IR_MEM_BO(IR_REG_STACK_POINTER, stack_offset), src_reg);
4411-
}
4411+
ir_emit_store_mem(ctx, type, IR_MEM_BO(IR_REG_STACK_POINTER, stack_offset), src_reg);
44124412
} else {
44134413
do_pass3 = 1;
44144414
}

‎ext/opcache/jit/ir/ir_dump.c‎

Lines changed: 43 additions & 74 deletions
Original file line numberDiff line numberDiff line change
@@ -162,39 +162,52 @@ void ir_dump_use_lists(const ir_ctx *ctx, FILE *f)
162162
}
163163
}
164164

165-
static int ir_dump_dessa_move(ir_ctx *ctx, uint8_t type, ir_ref from, ir_ref to)
165+
static void ir_dump_dessa_moves(const ir_ctx *ctx, int b, ir_block *bb, FILE *f)
166166
{
167-
FILE *f = ctx->data;
168-
int8_t reg;
169-
170-
if (IR_IS_CONST_REF(from)) {
171-
fprintf(f, "\tmov c_%d -> ", -from);
172-
} else if (from) {
173-
fprintf(f, "\tmov R%d", ctx->vregs[from]);
174-
if (ctx->live_intervals && ctx->live_intervals[ctx->vregs[from]]) {
175-
reg = ctx->live_intervals[ctx->vregs[from]]->reg;
176-
if (reg >= 0) {
177-
fprintf(f, " [%%%s]", ir_reg_name(reg, type));
167+
uint32_t succ;
168+
ir_block *succ_bb;
169+
ir_use_list *use_list;
170+
ir_ref k, i, *p, use_ref, input;
171+
ir_insn *use_insn;
172+
173+
IR_ASSERT(bb->successors_count == 1);
174+
succ = ctx->cfg_edges[bb->successors];
175+
succ_bb = &ctx->cfg_blocks[succ];
176+
IR_ASSERT(succ_bb->predecessors_count > 1);
177+
use_list = &ctx->use_lists[succ_bb->start];
178+
k = ir_phi_input_number(ctx, succ_bb, b);
179+
180+
for (i = 0, p = &ctx->use_edges[use_list->refs]; i < use_list->count; i++, p++) {
181+
use_ref = *p;
182+
use_insn = &ctx->ir_base[use_ref];
183+
if (use_insn->op == IR_PHI) {
184+
input = ir_insn_op(use_insn, k);
185+
if (IR_IS_CONST_REF(input)) {
186+
fprintf(f, "\t# DESSA MOV c_%d", -input);
187+
} else if (ctx->vregs[input] != ctx->vregs[use_ref]) {
188+
fprintf(f, "\t# DESSA MOV d_%d {R%d}", input, ctx->vregs[input]);
189+
} else {
190+
continue;
191+
}
192+
if (ctx->regs) {
193+
int8_t *regs = ctx->regs[use_ref];
194+
int8_t reg = regs[k];
195+
if (reg != IR_REG_NONE) {
196+
fprintf(f, " {%%%s%s}", ir_reg_name(IR_REG_NUM(reg), ctx->ir_base[input].type),
197+
(reg & (IR_REG_SPILL_LOAD|IR_REG_SPILL_SPECIAL)) ? ":load" : "");
198+
}
178199
}
179-
}
180-
fprintf(f, " -> ");
181-
} else {
182-
fprintf(f, "\tmov TMP -> ");
183-
}
184-
185-
if (to) {
186-
fprintf(f, "R%d", ctx->vregs[to]);
187-
if (ctx->live_intervals && ctx->live_intervals[ctx->vregs[to]]) {
188-
reg = ctx->live_intervals[ctx->vregs[to]]->reg;
189-
if (reg >= 0) {
190-
fprintf(f, " [%%%s]", ir_reg_name(reg, type));
200+
fprintf(f, " -> d_%d {R%d}", use_ref, ctx->vregs[use_ref]);
201+
if (ctx->regs) {
202+
int8_t reg = ctx->regs[use_ref][0];
203+
if (reg != IR_REG_NONE) {
204+
fprintf(f, " {%%%s%s}", ir_reg_name(IR_REG_NUM(reg), ctx->ir_base[use_ref].type),
205+
(reg & (IR_REG_SPILL_STORE|IR_REG_SPILL_SPECIAL)) ? ":store" : "");
206+
}
191207
}
208+
fprintf(f, "\n");
192209
}
193-
fprintf(f, "\n");
194-
} else {
195-
fprintf(f, "TMP\n");
196210
}
197-
return 1;
198211
}
199212

200213
void ir_dump_cfg(ir_ctx *ctx, FILE *f)
@@ -283,8 +296,7 @@ void ir_dump_cfg(ir_ctx *ctx, FILE *f)
283296
}
284297
}
285298
if (bb->flags & IR_BB_DESSA_MOVES) {
286-
ctx->data = f;
287-
ir_gen_dessa_moves(ctx, b, ir_dump_dessa_move);
299+
ir_dump_dessa_moves(ctx, b, bb, f);
288300
}
289301
}
290302
fprintf(f, "}\n");
@@ -621,50 +633,7 @@ void ir_dump_codegen(const ir_ctx *ctx, FILE *f)
621633
}
622634

623635
if (bb->flags & IR_BB_DESSA_MOVES) {
624-
uint32_t succ;
625-
ir_block *succ_bb;
626-
ir_use_list *use_list;
627-
ir_ref k, i, *p, use_ref, input;
628-
ir_insn *use_insn;
629-
630-
IR_ASSERT(bb->successors_count == 1);
631-
succ = ctx->cfg_edges[bb->successors];
632-
succ_bb = &ctx->cfg_blocks[succ];
633-
IR_ASSERT(succ_bb->predecessors_count > 1);
634-
use_list = &ctx->use_lists[succ_bb->start];
635-
k = ir_phi_input_number(ctx, succ_bb, b);
636-
637-
for (i = 0, p = &ctx->use_edges[use_list->refs]; i < use_list->count; i++, p++) {
638-
use_ref = *p;
639-
use_insn = &ctx->ir_base[use_ref];
640-
if (use_insn->op == IR_PHI) {
641-
input = ir_insn_op(use_insn, k);
642-
if (IR_IS_CONST_REF(input)) {
643-
fprintf(f, "\t# DESSA MOV c_%d", -input);
644-
} else if (ctx->vregs[input] != ctx->vregs[use_ref]) {
645-
fprintf(f, "\t# DESSA MOV d_%d {R%d}", input, ctx->vregs[input]);
646-
} else {
647-
continue;
648-
}
649-
if (ctx->regs) {
650-
int8_t *regs = ctx->regs[use_ref];
651-
int8_t reg = regs[k];
652-
if (reg != IR_REG_NONE) {
653-
fprintf(f, " {%%%s%s}", ir_reg_name(IR_REG_NUM(reg), ctx->ir_base[input].type),
654-
(reg & (IR_REG_SPILL_LOAD|IR_REG_SPILL_SPECIAL)) ? ":load" : "");
655-
}
656-
}
657-
fprintf(f, " -> d_%d {R%d}", use_ref, ctx->vregs[use_ref]);
658-
if (ctx->regs) {
659-
int8_t reg = ctx->regs[use_ref][0];
660-
if (reg != IR_REG_NONE) {
661-
fprintf(f, " {%%%s%s}", ir_reg_name(IR_REG_NUM(reg), ctx->ir_base[use_ref].type),
662-
(reg & (IR_REG_SPILL_STORE|IR_REG_SPILL_SPECIAL)) ? ":store" : "");
663-
}
664-
}
665-
fprintf(f, "\n");
666-
}
667-
}
636+
ir_dump_dessa_moves(ctx, b, bb, f);
668637
}
669638

670639
insn = &ctx->ir_base[bb->end];

0 commit comments

Comments
 (0)