[M68k] Fix requirements and operands for MOVE from/to CCR/SR

This fixes the defined CPU feature requirements for some of the MOVE
from/to CCR/SR instructions. Specifically, MOVE to CCR and MOVE from SR
are available to the whole 68000 family, except MOVE from SR requires
supervisor mode on 68010+.

On 68000, MOVE from SR is used instead of MOVE from CCR to move the
condition bits. A new feature predicate IsM68000 is added for any
lowering that needs to make this choice.

The operands on these instructions are also adjusted to not take a
destination for MOVE to CCR/SR (because the destination is invariable)
and to not take a source for MOVE from CCR/SR (because the source is
invariable).

Author: dansalvato

llvm/lib/Target/M68k/M68kInstrData.td

@@ -374,15 +374,15 @@ def MOVM32mp_P : MxMOVEM_RM_Pseudo<MxType32r, MxType32.POp>;
 /// --------------------------------------------------
 let Defs = [CCR] in {
 class MxMoveToCCR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
-    : MxInst<(outs CCRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
+    : MxInst<(outs), (ins MEMOp:$src), "move.w\t$src, %ccr", []> {
   let Inst = (ascend
     (descend 0b0100010011, SRC_ENC.EA),
     SRC_ENC.Supplement
   );
 }
 
 class MxMoveToCCRPseudo<MxOperand MEMOp>
-    : MxPseudo<(outs CCRC:$dst), (ins MEMOp:$src)>;
+    : MxPseudo<(outs), (ins MEMOp:$src)>;
 } // let Defs = [CCR]
 
 let mayLoad = 1 in
@@ -405,13 +405,13 @@ def MOV8cd  : MxMoveToCCRPseudo<MxOp8AddrMode_d.Op>;
 /// --------------------------------------------------
 let Uses = [CCR] in {
 class MxMoveFromCCR_R
-    : MxInst<(outs MxDRD16:$dst), (ins CCRC:$src), "move.w\t$src, $dst", []>,
+    : MxInst<(outs MxDRD16:$dst), (ins), "move.w\t%ccr, $dst", []>,
       Requires<[ AtLeastM68010 ]> {
   let Inst = (descend 0b0100001011, MxEncAddrMode_d<"dst">.EA);
 }
 
 class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
-    : MxInst<(outs), (ins MEMOp:$dst, CCRC:$src), "move.w\t$src, $dst", []>,
+    : MxInst<(outs), (ins MEMOp:$dst), "move.w\t%ccr, $dst", []>,
       Requires<[ AtLeastM68010 ]> {
   let Inst = (ascend
     (descend 0b0100001011, DST_ENC.EA),
@@ -420,9 +420,9 @@ class MxMoveFromCCR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
 }
 
 class MxMoveFromCCRPseudo<MxOperand MEMOp>
-    : MxPseudo<(outs), (ins MEMOp:$dst, CCRC:$src)>;
+    : MxPseudo<(outs), (ins MEMOp:$dst)>;
 class MxMoveFromCCR_RPseudo<MxOperand MEMOp>
-    : MxPseudo<(outs MEMOp:$dst), (ins CCRC:$src)>;
+    : MxPseudo<(outs MEMOp:$dst), (ins)>;
 } // let Uses = [CCR]
 
 let mayStore = 1 in
@@ -447,7 +447,7 @@ def MOV8dc  : MxMoveFromCCR_RPseudo<MxOp8AddrMode_d.Op>;
 /// --------------------------------------------------
 let Defs = [SR] in {
 class MxMoveToSR<MxOperand MEMOp, MxEncMemOp SRC_ENC>
-    : MxInst<(outs SRC:$dst), (ins MEMOp:$src), "move.w\t$src, $dst", []> {
+    : MxInst<(outs), (ins MEMOp:$src), "move.w\t$src, %sr", []> {
   let Inst = (ascend
     (descend 0b0100011011, SRC_ENC.EA),
     SRC_ENC.Supplement
@@ -470,16 +470,17 @@ def MOV16sd : MxMoveToSR<MxOp16AddrMode_d.Op, MxMoveSrcOpEnc_d>;
 ///                               | EFFECTIVE ADDRESS
 ///  0  1  0  0  0  0  0  0  1  1 |   MODE  |   REG
 /// --------------------------------------------------
+
+// MoveFromSR works on 68010+ but it causes an exception unless in
+// supervisor mode. But on 68000, MoveFromSR is the *only* way to move CCR.
 let Uses = [SR] in {
 class MxMoveFromSR_R
-    : MxInst<(outs MxDRD16:$dst), (ins SRC:$src), "move.w\t$src, $dst", []>,
-      Requires<[ AtLeastM68010 ]> {
+    : MxInst<(outs MxDRD16:$dst), (ins), "move.w\t%sr, $dst", []> {
   let Inst = (descend 0b0100000011, MxEncAddrMode_d<"dst">.EA);
 }
 
 class MxMoveFromSR_M<MxOperand MEMOp, MxEncMemOp DST_ENC>
-    : MxInst<(outs), (ins MEMOp:$dst, SRC:$src), "move.w\t$src, $dst", []>,
-      Requires<[ AtLeastM68010 ]> {
+    : MxInst<(outs), (ins MEMOp:$dst), "move.w\t%sr, $dst", []> {
   let Inst = (ascend
     (descend 0b0100000011, DST_ENC.EA),
     DST_ENC.Supplement

llvm/lib/Target/M68k/M68kInstrInfo.td

@@ -465,6 +465,9 @@ def IsPIC        : Predicate<"TM.isPositionIndependent()">;
 def IsNotPIC     : Predicate<"!TM.isPositionIndependent()">;
 
 // ISA versions
+def IsM68000 : Predicate<"Subtarget->isM68000()">,
+                            AssemblerPredicate<(all_of FeatureISA00)>;
+
 foreach i = [0,1,2,4,6] in
 def AtLeastM680 # i # "0" : Predicate<"Subtarget->atLeastM680"#i#"0()">,
                             AssemblerPredicate<(all_of

llvm/lib/Target/M68k/M68kSubtarget.h

@@ -84,6 +84,7 @@ class M68kSubtarget : public M68kGenSubtargetInfo {
   /// of function is auto generated by tblgen.
   void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
 
+  bool isM68000() const { return SubtargetKind == M00; }
   bool atLeastM68000() const { return SubtargetKind >= M00; }
   bool atLeastM68010() const { return SubtargetKind >= M10; }
   bool atLeastM68020() const { return SubtargetKind >= M20; }