[M68k] Fix backwards BTST condition

dansalvato · dansalvato · commit f608373e0b75 · 2025-08-12T11:24:01.000-06:00
diff --git a/llvm/lib/Target/M68k/M68kISelLowering.cpp b/llvm/lib/Target/M68k/M68kISelLowering.cpp
@@ -1666,7 +1666,7 @@ static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,
   SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);
 
   // NOTE BTST sets CCR.Z flag
-  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;
+  M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_EQ : M68k::COND_NE;
   return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,
                      DAG.getConstant(Cond, DL, MVT::i8), BTST);
 }

Original file line number	Diff line number	Diff line change
`@@ -1666,7 +1666,7 @@ static SDValue getBitTestCondition(SDValue Src, SDValue BitNo, ISD::CondCode CC,`
`1666`	`1666`	`SDValue BTST = DAG.getNode(M68kISD::BTST, DL, MVT::i32, Src, BitNo);`
`1667`	`1667`
`1668`	`1668`	`// NOTE BTST sets CCR.Z flag`
`1669`		`- M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_NE : M68k::COND_EQ;`
	`1669`	`+ M68k::CondCode Cond = CC == ISD::SETEQ ? M68k::COND_EQ : M68k::COND_NE;`
`1670`	`1670`	`return DAG.getNode(M68kISD::SETCC, DL, MVT::i8,`
`1671`	`1671`	`DAG.getConstant(Cond, DL, MVT::i8), BTST);`
`1672`	`1672`	`}`