Draft: Add s-mode CLIC interrupt testcases

This is a draft version of the s-mode (Ssclic) CLIC interrupt testcases using clint MSW and MTIMER macros.

Note: pulls are not yet available for spike or sail that support CLIC but these testcases should help enable their development. 

This pull requires:
riscv-software-src/riscv-config#169, 
riscv-software-src/riscof#106
riscv-software-src/riscv-isa-sim#1596

To include s-mode CLIC interrupt tests in riscof testlist flow, add Ssclic to riscof yaml file, e.g.:
spike/spike_isa.yaml:
  ISA: RV32IMCZicsr_Zifencei_Ssclic


Signed-off-by: Dan Smathers <dan.smathers@seagate.com>

Author: dansmathers