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ADD smclint testcase summary
Signed-off-by: Dan Smathers <dan.smathers@seagate.com>
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‎riscv-test-suite/rv32i_m/Smclint/src/smclint.adoc‎

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==== msw-01.S
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.Description: tests if RVMODEL_SET_MSW_INT is working, hangs in infinite loop otherwise
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger m-mode handler
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- clear interrupt
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- set mepc to finish
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = <EMPTY>
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = <EMPTY>
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RVMODEL_WFI = jump_to_self
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----
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Coverage
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----
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msip trigger | verify RVMODEL_SET_MSW_INT trigger
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msip clear | verify RVMODEL_CLEAR_MSW_INT clear
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mip.msip | verify mip signature 0/1
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mcause | verify machine software interrupt signature
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mstatus | verify mstatus.mie/mpie/mpp signature in interrupt handler and after mret
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mtvec | verify interrupt uses mtvec to calculate pc of interrupt handler (direct)
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mepc | verify mepc location is jump_to_self location
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----
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==== mtimer-01.S
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.Description: tests if RVMODEL_SET_MTIMER_INT is working, hangs in infinite loop otherwise
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger m-mode handler
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- clear interrupt
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- set mepc to finish
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_INT1 = RVMODEL_SET_MTIMER_INT
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RVMODEL_SET_INT2 = <EMPTY>
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MTIMER_INT
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RVMODEL_CLEAR_INT2 = <EMPTY>
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RVMODEL_WFI = jump_to_self
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----
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Coverage
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----
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mtip trigger | verify RVMODEL_SET_MTIMER_INT trigger
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mtip clear | verify RVMODEL_CLEAR_MTIMER_INT clear
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mip.mtip | verify mip signature 0/1
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mcause | verify machine timer interrupt signature
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mstatus | verify mstatus.mie/mpie/mpp signature in interrupt handler and after mret
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mtvec | verify interrupt uses mtvec to calculate pc of interrupt handler (direct)
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mepc | verify mepc location is jump_to_self location
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----
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==== nomint-01.S
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.Description: expect interrupts will not trigger in m-mode unless mstatus.mie is set
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- enable mie
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- generate interrupts
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- nop
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- jump to finish
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[%autofit]
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----
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RVMODEL_MSTATUS_MIE = 0
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT
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RVMODEL_WFI = nop
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----
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Coverage
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----
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mstatus.mie | verify no interrupt occurs in m-mode if mstatus.mie is 0
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----
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==== nomint-02.S
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.Description: expect interrupts will not trigger in m-mode unless mie.x is set
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- generate interrupts
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- enable mstatus.mie
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- nop
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- jump to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = 0
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT
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RVMODEL_WFI = nop
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----
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Coverage
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----
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mie.msip | verify no msw interrupt occurs if mie.msip is 0
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mie.mtip | verify no mtimer interrupt occurs if mie.mtip is 0
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----
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==== wfi-01.S
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.Description: expect wfi to behave like a nop when a single interrupt is pending when mstatus.mie is disabled
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- enable mie CSR
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- generate interrupts
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- wfi
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- wakeup
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- jump to finish
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[%autofit]
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----
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RVMODEL_MSTATUS_MIE = 0
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT
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----
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Coverage
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----
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mstatus.mie | verify no interrupt occurs in m-mode if mstatus.mie is 0
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wfi | verify wakeup/nop occurs with mstatus.mie = 0
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wfi | verify wakeup/nop occurs with pending interrupt
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----
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==== direct-01.S
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.Description: trigger, clear, retrigger same interrupt.
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger m-mode handler
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- clear 1st interrupt
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- generate interrupt
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- trigger 2nd m-mode handler
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- clear 2nd interrupt
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- set mepc to finish
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT
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----
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Coverage - same as msw-01.S plus
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----
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mtvec.mode | verify direct mode is used to handle interrupt
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msip retrigger | verify after mstatus.mie is enabled in interrupt handler, msip will retrigger
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----
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==== direct-02.S
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.Description: trigger, clear, retrigger single interrupt, no 2nd clear.
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Stimulates pending interrupt after setting mstatus.mpie followed by mret
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mstatus.mie should be cleared after mret so pending interrupt is not taken
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger m-mode handler
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- clear 1st interrupt
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- generate interrupt
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- trigger 2nd m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = <EMPTY>
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----
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Coverage - same as msw-01.S plus
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----
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msip retrigger | verify after mstatus.mie is enabled after mret, msip will retrigger
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----
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==== vectored-01.S
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.Description: trigger, clear, retrigger single interrupt, vectored-mode.
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger vectored m-mode handler
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- clear 1st interrupt
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- generate interrupt
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- trigger 2nd vectored m-mode handler
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- clear 2nd interrupt
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- set mepc to finish
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_MTVEC_MODE = 1
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT
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----
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Coverage - same as msw-01.S plus
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----
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mtvec.mode | verify vectored mode is used to handle interrupt
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msip retrigger | verify after mstatus.mie is enabled in interrupt handler, msip will retrigger
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----
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==== vectored-02.S
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.Description: trigger, clear, retrigger single interrupt, no 2nd clear.
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Stimulates pending interrupt after setting mstatus.mpie followed by mret, vectored-mode.
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mstatus.mie should be cleared after mret so pending interrupt is not taken
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger vectored m-mode handler
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- clear 1st interrupt
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- generate interrupt
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- trigger 2nd vectored m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_MTVEC_MODE = 1
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = RVMODEL_CLEAR_MSW_INT
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RVMODEL_CLEAR_INT2 = <EMPTY>
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----
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Coverage - same as msw-01.S plus
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----
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mtvec.mode | verify vectored mode is used to handle interrupt
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msip retrigger | verify after mstatus.mie is enabled after mret, msip will retrigger
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----
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==== ecall-01.S
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.Description: trigger, clear, set interrupt pending, ecall
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Stimulates ecall within an interrupt handler to stimulate mcause.interrupt toggling
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mstatus.mie should be cleared after mret so pending interrupt is not taken
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- enable mie CSR
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- generate interrupt
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- enable mstatus.mie
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- trigger m-mode vectored interrupt handler
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- ecall instruction to trigger (direct) exception handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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- re-trigger interrupt
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[%autofit]
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----
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RVMODEL_SET_MIE = MIE_MSIE
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RVMODEL_MTVEC_MODE = 1
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = <EMPTY>
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RVMODEL_CLEAR_INT1 = <EMPTY>
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RVMODEL_CLEAR_INT2 = <EMPTY>
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RVMODEL_ECALL = ecall
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----
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Coverage - same as msw-01.S plus
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----
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mtvec.mode | verify vectored mode is used to handle interrupt
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mcause.interrupt 0/1 | verify ecall toggles mcause.interrupt, uses direct exception handler
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----
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==== level-01.S
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.Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, mtvec.mode=direct
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- enable mie CSR
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- generate interrupt 1
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- enable mstatus.mie
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- trigger m-mode handler
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- generate interrupt 2 (both interrupts now pending)
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- trigger 2nd m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT
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RVMODEL_CLEAR_INT1 = <EMPTY>
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT
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----
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Coverage
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----
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Interrupt ordering - both interrupts asserted in msw interrupt handler
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----
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==== level-02.S
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.Description: verify interrupt level order, swap 2 interrupt order, mtvec.mode=direct
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- enable mie CSR
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- generate interrupt 1
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- enable mstatus.mie
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- trigger m-mode handler
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- generate interrupt 2 (both interrupts now pending)
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- set mstatus.mie
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- trigger 2nd m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_SET_INT1 = RVMODEL_SET_MTIMER_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = <EMPTY>
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT
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----
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----
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Interrupt ordering - both interrupts asserted in mtimer interrupt handler
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----
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==== level-03.S
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.Description: verify interrupt level order, 2 interrupts asserted in 1st interrupt handler, mtvec.mode=vectored
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- enable mie CSR
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- generate interrupt 1
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- enable mstatus.mie
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- trigger vectored m-mode handler
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- generate interrupt 2 (both interrupts now pending)
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- set mstatus.mie
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- trigger 2nd vectored m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_MTVEC_MODE = 1
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RVMODEL_SET_INT1 = RVMODEL_SET_MSW_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MTIMER_INT
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RVMODEL_CLEAR_INT1 = <EMPTY>
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MTIMER_INT
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----
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Coverage
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----
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mtvec.mode | verify vectored mode is used to handle interrupt, signature of higher priority interrupt
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Interrupt ordering | both interrupts asserted in msw interrupt handler
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----
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==== level-04.S
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.Description: verify interrupt level order, swap 2 interrupt order, mtvec.mode=vectored
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- enable mie CSR
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- generate interrupt 1
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- enable mstatus.mie
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- trigger vectored m-mode handler
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- generate interrupt 2 (both interrupts now pending)
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- set mstatus.mie
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- trigger 2nd vectored m-mode handler
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- set mepc to finish
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- clear mstatus.mpie
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- mret to finish
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[%autofit]
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----
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RVMODEL_MTVEC_MODE = 1
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RVMODEL_SET_INT1 = RVMODEL_SET_MTIMER_INT
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RVMODEL_SET_INT2 = RVMODEL_SET_MSW_INT
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RVMODEL_CLEAR_INT1 = <EMPTY>
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RVMODEL_CLEAR_INT2 = RVMODEL_CLEAR_MSW_INT
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----
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Coverage
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----
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mtvec.mode | verify vectored mode is used to handle interrupt, signature of higher priority interrupt
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Interrupt ordering | both interrupts asserted in mtimer interrupt handler
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----

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