status

Author: daquintero

docs/examples/04_spice_cosimulation/netlist.raw

@@ -1,16 +1,16 @@
 # # `piel` Electronic-Photonic Co-Design - Full Flow Demo
 
 # <div style="padding: 10px; border-radius: 5px;">
-# <strong>⚠️ Warning:</strong> This example requires using the piel nix environment which are locally available when cloning and installing the `stable` verision of the github source code. See example setup as follows
+# <strong>⚠️ Warning:</strong> This example requires the <code>piel-nix</code> tools environment.
+# <a href="https://piel.readthedocs.io/en/latest/sections/environment/index.html" target="_blank">See environment configuration documentation</a>.
 # </div>
-#
-# Note that this is only CI tested in an ubuntu environment:
-# ```
-# git clone https://github.com/daquintero/piel.git
-# source scripts/install_piel_nix.sh
-# ```
-#
-# You can verify you have the tools required by running the following magic cells:
+
+# + active=""
+# !git clone https://github.com/daquintero/piel.git
+# !cd piel/
+# !source scripts/install_piel_nix.sh
+# !nix develop .
+# -
 
 # ! which openlane
 

docs/examples/07_full_flow_demo_electronic_photonic/07_full_flow_demo_electronic_photonic.py

@@ -4,49 +4,49 @@
 (* generator = "Amaranth" *)
 module top(bit_phase_0, bit_phase_1, input_fock_state_str);
   reg \$auto$verilog_backend.cc:2334:dump_module$1  = 0;
-  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_0;
   reg [4:0] bit_phase_0;
-  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
+  (* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:86" *)
   output [4:0] bit_phase_1;
   reg [4:0] bit_phase_1;
-  (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
+  (* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:82" *)
   input [2:0] input_fock_state_str;
   wire [2:0] input_fock_state_str;
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_0 = 5'h00;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_0 = 5'h1f;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_0 = 5'h00;
     endcase
   end
   always @* begin
     if (\$auto$verilog_backend.cc:2334:dump_module$1 ) begin end
     (* full_case = 32'd1 *)
-    (* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
+    (* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:112" *)
     casez (input_fock_state_str)
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h4:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h1:
           bit_phase_1 = 5'h1f;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:115" */
       3'h2:
           bit_phase_1 = 5'h00;
-      /* src = "/nix/store/spmis1i5ppqaji3xk4ypfbknqzs93pls-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
+      /* src = "/nix/store/gi3w8lbvfd4x4gf9m2shpybb58mdkzrr-python3.11-piel-0.1.0/lib/python3.11/site-packages/piel/tools/amaranth/construct.py:124" */
       default:
           bit_phase_1 = 5'h00;
     endcase