Update README.md

Author: mbabaie

README.md

@@ -7,4 +7,4 @@ the actual hardware providing DRAM cache, such as Intel’s Cascade Lake, in whi
 memory sharing the same bus. We model a unified DRAM cache controller (UDCC) in gem5 to control a DRAM device (which acts as a cache of 
 the main memory) and an NVM device (which serves as the main memory in the system) and both devices share a data bus.
 
-For test, you can look at the sample script: cascadeLake_dram_cache_script.py
+For testing, you can look at the sample script: cascadeLake_dram_cache_script.py