mem: first version of second class (2 interfaces)

Change-Id: I999a7f15b795a97da247f14b5069cec5143c4945

Author: mbabaie

src/mem/SConscript

@@ -49,6 +49,7 @@ SimObject('Bridge.py', sim_objects=['Bridge'])
 SimObject('SysBridge.py', sim_objects=['SysBridge'])
 DebugFlag('SysBridge')
 SimObject('MemCtrl.py', sim_objects=['MemCtrl'], enums=['MemSched'])
+SimObject('HetMemCtrl.py', sim_objects=['HetMemCtrl'], enums=['HetMemSched'])
 SimObject('MemInterface.py', sim_objects=['MemInterface'], enums=['AddrMap'])
 SimObject('DRAMInterface.py', sim_objects=['DRAMInterface'],
         enums=['PageManage'])
@@ -135,6 +136,7 @@ DebugFlag('ExternalPort')
 DebugFlag('HtmMem', 'Hardware Transactional Memory (Mem side)')
 DebugFlag('LLSC')
 DebugFlag('MemCtrl')
+DebugFlag('HetMemCtrl')
 DebugFlag('MMU')
 DebugFlag('MemoryAccess')
 DebugFlag('PacketQueue')