mem: rename MemCtrl to HeteroMemCtrl

Change-Id: I5203c7c45edaa5ce2bc8f7d62cea8abe28605696

Author: aakahlow

configs/common/MemConfig.py

@@ -235,7 +235,7 @@ def config_mem(options, system):
                 # Create a controller if not sharing a channel with DRAM
                 # in which case the controller has already been created
                 if not opt_hybrid_channel:
-                    mem_ctrl = m5.objects.MemCtrl()
+                    mem_ctrl = m5.objects.HeteroMemCtrl()
                     mem_ctrl.nvm = nvm_intf
 
                     mem_ctrls.append(mem_ctrl)

configs/dram/lat_mem_rd.py

@@ -119,7 +119,7 @@
 
     # the following assumes that we are using the native DRAM
     # controller, check to be sure
-    if isinstance(ctrl, m5.objects.MemCtrl):
+    if isinstance(ctrl, m5.objects.HeteroMemCtrl):
         # make the DRAM refresh interval sufficiently infinite to avoid
         # latency spikes
         ctrl.tREFI = '100s'

configs/nvm/sweep_hybrid.py

@@ -117,8 +117,8 @@
 
 # the following assumes that we are using the native controller
 # with NVM and DRAM interfaces, check to be sure
-if not isinstance(system.mem_ctrls[0], m5.objects.MemCtrl):
-    fatal("This script assumes the controller is a MemCtrl subclass")
+if not isinstance(system.mem_ctrls[0], m5.objects.HeteroMemCtrl):
+    fatal("This script assumes the controller is a HeteroMemCtrl subclass")
 if not isinstance(system.mem_ctrls[0].dram, m5.objects.DRAMInterface):
     fatal("This script assumes the first memory is a DRAMInterface subclass")
 if not isinstance(system.mem_ctrls[0].nvm, m5.objects.NVMInterface):

configs/ruby/GPU_VIPER.py

@@ -523,7 +523,7 @@ def construct_gpudirs(options, system, ruby_system, network):
             int(math.log(options.dgpu_num_dirs, 2)), options.cacheline_size,
             xor_low_bit)
         if issubclass(mem_type, DRAMInterface):
-            mem_ctrl = m5.objects.MemCtrl(dram = dram_intf)
+            mem_ctrl = m5.objects.HeteroMemCtrl(dram = dram_intf)
         else:
             mem_ctrl = dram_intf
 

src/mem/MemCtrl.py src/mem/HeteroMemCtrl.pysrc/mem/MemCtrl.py renamed to src/mem/HeteroMemCtrl.py

@@ -43,14 +43,14 @@
 from m5.objects.SimpleMemCtrl import *
 
 
-# MemCtrl controls a dram and an nvm interface
+# HeteroMemCtrl controls a dram and an nvm interface
 # Both memory interfaces share the data and command bus
-class MemCtrl(SimpleMemCtrl):
-    type = 'MemCtrl'
-    cxx_header = "mem/mem_ctrl.hh"
-    cxx_class = 'gem5::memory::MemCtrl'
+class HeteroMemCtrl(SimpleMemCtrl):
+    type = 'HeteroMemCtrl'
+    cxx_header = "mem/hetero_mem_ctrl.hh"
+    cxx_class = 'gem5::memory::HeteroMemCtrl'
 
     # Interface to nvm memory media
-    # The dram interface `dram` used by MemCtrl is defined in
+    # The dram interface `dram` used by HeteroMemCtrl is defined in
     # the SimpleMemCtrl
     nvm = Param.NVMInterface("NVM memory interface to use")

src/mem/SConscript

@@ -50,7 +50,7 @@ SimObject('SysBridge.py', sim_objects=['SysBridge'])
 DebugFlag('SysBridge')
 SimObject('SimpleMemCtrl.py', sim_objects=['SimpleMemCtrl'],
         enums=['MemSched'])
-SimObject('MemCtrl.py', sim_objects=['MemCtrl'])
+SimObject('HeteroMemCtrl.py', sim_objects=['HeteroMemCtrl'])
 SimObject('MemInterface.py', sim_objects=['MemInterface'], enums=['AddrMap'])
 SimObject('DRAMInterface.py', sim_objects=['DRAMInterface'],
         enums=['PageManage'])

src/mem/mem_ctrl.cc src/mem/hetero_mem_ctrl.ccsrc/mem/mem_ctrl.cc renamed to src/mem/hetero_mem_ctrl.cc

@@ -38,15 +38,14 @@
  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  */
 
-#include "mem/mem_ctrl.hh"
-
 #include "base/trace.hh"
 #include "debug/DRAM.hh"
 #include "debug/Drain.hh"
 #include "debug/MemCtrl.hh"
 #include "debug/NVM.hh"
 #include "debug/QOS.hh"
 #include "mem/dram_interface.hh"
+#include "mem/mem_ctrl.hh"
 #include "mem/mem_interface.hh"
 #include "mem/nvm_interface.hh"
 #include "sim/system.hh"
@@ -57,7 +56,7 @@ namespace gem5
 namespace memory
 {
 
-MemCtrl::MemCtrl(const MemCtrlParams &p) :
+HeteroMemCtrl::HeteroMemCtrl(const HeteroMemCtrlParams &p) :
     SimpleMemCtrl(p),
     nvm(p.nvm)
 {
@@ -66,9 +65,9 @@ MemCtrl::MemCtrl(const MemCtrlParams &p) :
     writeQueue.resize(p.qos_priorities);
 
     fatal_if(dynamic_cast<DRAMInterface*>(dram) == nullptr,
-             "MemCtrl's dram interface must be of type DRAMInterface.\n");
+            "HeteroMemCtrl's dram interface must be of type DRAMInterface.\n");
     fatal_if(dynamic_cast<NVMInterface*>(nvm) == nullptr,
-             "MemCtrl's nvm interface must be of type NVMInterface.\n");
+            "HeteroMemCtrl's nvm interface must be of type NVMInterface.\n");
 
     // hook up interfaces to the controller
     dram->setCtrl(this, commandWindow);
@@ -88,7 +87,7 @@ MemCtrl::MemCtrl(const MemCtrlParams &p) :
 }
 
 Tick
-MemCtrl::recvAtomic(PacketPtr pkt)
+HeteroMemCtrl::recvAtomic(PacketPtr pkt)
 {
     Tick latency = 0;
 
@@ -104,7 +103,7 @@ MemCtrl::recvAtomic(PacketPtr pkt)
 }
 
 bool
-MemCtrl::recvTimingReq(PacketPtr pkt)
+HeteroMemCtrl::recvTimingReq(PacketPtr pkt)
 {
     // This is where we enter from the outside world
     DPRINTF(MemCtrl, "recvTimingReq: request %s addr %#x size %d\n",
@@ -193,7 +192,7 @@ MemCtrl::recvTimingReq(PacketPtr pkt)
 }
 
 void
-MemCtrl::processRespondEvent(MemInterface* mem_intr,
+HeteroMemCtrl::processRespondEvent(MemInterface* mem_intr,
                         MemPacketQueue& queue,
                         EventFunctionWrapper& resp_event)
 {
@@ -208,7 +207,7 @@ MemCtrl::processRespondEvent(MemInterface* mem_intr,
 }
 
 MemPacketQueue::iterator
-MemCtrl::chooseNext(MemPacketQueue& queue, Tick extra_col_delay,
+HeteroMemCtrl::chooseNext(MemPacketQueue& queue, Tick extra_col_delay,
                     MemInterface* mem_int)
 {
     // This method does the arbitration between requests.
@@ -246,7 +245,7 @@ MemCtrl::chooseNext(MemPacketQueue& queue, Tick extra_col_delay,
 }
 
 std::pair<MemPacketQueue::iterator, Tick>
-MemCtrl::chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay,
+HeteroMemCtrl::chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay,
                           MemInterface* mem_intr)
 {
 
@@ -274,9 +273,9 @@ MemCtrl::chooseNextFRFCFS(MemPacketQueue& queue, Tick extra_col_delay,
 
 
 Tick
-MemCtrl::doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr)
+HeteroMemCtrl::doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr)
 {
-    // mem_intr will be dram by default in MemCtrl
+    // mem_intr will be dram by default in HeteroMemCtrl
 
     // When was command issued?
     Tick cmd_at;
@@ -296,9 +295,9 @@ MemCtrl::doBurstAccess(MemPacket* mem_pkt, MemInterface* mem_intr)
 }
 
 bool
-MemCtrl::memBusy(MemInterface* mem_intr) {
+HeteroMemCtrl::memBusy(MemInterface* mem_intr) {
 
-    // mem_intr in case of MemCtrl will always be dram
+    // mem_intr in case of HeteroMemCtrl will always be dram
 
     // check ranks for refresh/wakeup - uses busStateNext, so done after
     // turnaround decisions
@@ -324,41 +323,41 @@ MemCtrl::memBusy(MemInterface* mem_intr) {
 }
 
 void
-MemCtrl::nonDetermReads(MemInterface* mem_intr)
+HeteroMemCtrl::nonDetermReads(MemInterface* mem_intr)
 {
     // mem_intr by default points to dram in case
-    // of MemCtrl, therefore, calling nonDetermReads
+    // of HeteroMemCtrl, therefore, calling nonDetermReads
     // from SimpleMemCtrl using nvm interace
     SimpleMemCtrl::nonDetermReads(nvm);
 }
 
 bool
-MemCtrl::nvmWriteBlock(MemInterface* mem_intr)
+HeteroMemCtrl::nvmWriteBlock(MemInterface* mem_intr)
 {
     // mem_intr by default points to dram in case
-    // of MemCtrl, therefore, calling nvmWriteBlock
+    // of HeteroMemCtrl, therefore, calling nvmWriteBlock
     // from SimpleMemCtrl using nvm interface
     return SimpleMemCtrl::nvmWriteBlock(nvm);
 }
 
 Tick
-MemCtrl::minReadToWriteDataGap()
+HeteroMemCtrl::minReadToWriteDataGap()
 {
     return std::min(dram->minReadToWriteDataGap(),
                     nvm->minReadToWriteDataGap());
 }
 
 Tick
-MemCtrl::minWriteToReadDataGap()
+HeteroMemCtrl::minWriteToReadDataGap()
 {
     return std::min(dram->minWriteToReadDataGap(),
                     nvm->minWriteToReadDataGap());
 }
 
 Addr
-MemCtrl::burstAlign(Addr addr, MemInterface* mem_intr) const
+HeteroMemCtrl::burstAlign(Addr addr, MemInterface* mem_intr) const
 {
-    // mem_intr will point to dram interface in MemCtrl
+    // mem_intr will point to dram interface in HeteroMemCtrl
     if (mem_intr->getAddrRange().contains(addr)) {
         return (addr & ~(Addr(mem_intr->bytesPerBurst() - 1)));
     } else {
@@ -368,9 +367,9 @@ MemCtrl::burstAlign(Addr addr, MemInterface* mem_intr) const
 }
 
 bool
-MemCtrl::pktSizeCheck(MemPacket* mem_pkt, MemInterface* mem_intr) const
+HeteroMemCtrl::pktSizeCheck(MemPacket* mem_pkt, MemInterface* mem_intr) const
 {
-    // mem_intr will point to dram interface in MemCtrl
+    // mem_intr will point to dram interface in HeteroMemCtrl
     if (mem_pkt->isDram()) {
         return (mem_pkt->size <= mem_intr->bytesPerBurst());
     } else {
@@ -379,7 +378,7 @@ MemCtrl::pktSizeCheck(MemPacket* mem_pkt, MemInterface* mem_intr) const
 }
 
 void
-MemCtrl::recvFunctional(PacketPtr pkt)
+HeteroMemCtrl::recvFunctional(PacketPtr pkt)
 {
     bool found;
 
@@ -395,7 +394,7 @@ MemCtrl::recvFunctional(PacketPtr pkt)
 }
 
 bool
-MemCtrl::allIntfDrained() const
+HeteroMemCtrl::allIntfDrained() const
 {
     // ensure dram is in power down and refresh IDLE states
     bool dram_drained = dram->allRanksDrained();
@@ -406,7 +405,7 @@ MemCtrl::allIntfDrained() const
 }
 
 DrainState
-MemCtrl::drain()
+HeteroMemCtrl::drain()
 {
     // if there is anything in any of our internal queues, keep track
     // of that as well
@@ -432,7 +431,7 @@ MemCtrl::drain()
 }
 
 void
-MemCtrl::drainResume()
+HeteroMemCtrl::drainResume()
 {
     if (!isTimingMode && system()->isTimingMode()) {
         // if we switched to timing mode, kick things into action,
@@ -450,7 +449,7 @@ MemCtrl::drainResume()
 }
 
 AddrRangeList
-MemCtrl::getAddrRanges()
+HeteroMemCtrl::getAddrRanges()
 {
     AddrRangeList ranges;
     ranges.push_back(dram->getAddrRange());

src/mem/mem_ctrl.hh src/mem/hetero_mem_ctrl.hhsrc/mem/mem_ctrl.hh renamed to src/mem/hetero_mem_ctrl.hh

@@ -40,21 +40,21 @@
 
 /**
  * @file
- * MemCtrl declaration
+ * HeteroMemCtrl declaration
  */
 
-#ifndef __MEM_CTRL_HH__
-#define __MEM_CTRL_HH__
+#ifndef __HETERO_MEM_CTRL_HH__
+#define __HETERO_MEM_CTRL_HH__
 
 #include "mem/simple_mem_ctrl.hh"
-#include "params/MemCtrl.hh"
+#include "params/HeteroMemCtrl.hh"
 
 namespace gem5
 {
 
 namespace memory
 {
-class MemCtrl : public SimpleMemCtrl
+class HeteroMemCtrl : public SimpleMemCtrl
 {
   private:
 
@@ -120,7 +120,7 @@ class MemCtrl : public SimpleMemCtrl
 
   public:
 
-    MemCtrl(const MemCtrlParams &p);
+    HeteroMemCtrl(const HeteroMemCtrlParams &p);
 
     bool allIntfDrained() const override;
     DrainState drain() override;
@@ -137,4 +137,4 @@ class MemCtrl : public SimpleMemCtrl
 } // namespace memory
 } // namespace gem5
 
-#endif //__MEM_CTRL_HH__
+#endif //__HETERO_MEM_CTRL_HH__