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| 1 | +# Copyright (c) 2021 The Regents of the University of California |
| 2 | +# All rights reserved. |
| 3 | +# |
| 4 | +# Redistribution and use in source and binary forms, with or without |
| 5 | +# modification, are permitted provided that the following conditions are |
| 6 | +# met: redistributions of source code must retain the above copyright |
| 7 | +# notice, this list of conditions and the following disclaimer; |
| 8 | +# redistributions in binary form must reproduce the above copyright |
| 9 | +# notice, this list of conditions and the following disclaimer in the |
| 10 | +# documentation and/or other materials provided with the distribution; |
| 11 | +# neither the name of the copyright holders nor the names of its |
| 12 | +# contributors may be used to endorse or promote products derived from |
| 13 | +# this software without specific prior written permission. |
| 14 | +# |
| 15 | +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| 16 | +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| 17 | +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| 18 | +# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| 19 | +# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| 20 | +# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| 21 | +# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| 22 | +# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| 23 | +# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| 24 | +# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| 25 | +# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| 26 | + |
| 27 | +from abc import ABCMeta, abstractmethod |
| 28 | +from .mem_mode import MemMode |
| 29 | + |
| 30 | +from m5.objects import System, Port, IOXBar, ClockDomain |
| 31 | + |
| 32 | +from ..isas import ISA |
| 33 | +from ..coherence_protocol import CoherenceProtocol |
| 34 | + |
| 35 | +from typing import List |
| 36 | + |
| 37 | + |
| 38 | +class AbstractBoard(System): |
| 39 | + """The abstract board interface. |
| 40 | +
|
| 41 | + Boards are used as the object which can connect together all other |
| 42 | + components. This abstract class defines the external interface that other |
| 43 | + boards must provide. Boards can be specialized for different ISAs or system |
| 44 | + designs (e.g., core counts, cache types, memory channels, I/O devices, etc) |
| 45 | +
|
| 46 | + In addition to providing the place that system components are connected, |
| 47 | + the board also exposes an interface for the caches, processor, and memory |
| 48 | + to interact. |
| 49 | +
|
| 50 | + The board also exposes an interface to set up I/O devices which needs to be |
| 51 | + specialized for each ISA and/or platform. |
| 52 | +
|
| 53 | + Board inherits from System and can therefore be used as a System simobject |
| 54 | + when required. |
| 55 | + """ |
| 56 | + |
| 57 | + __metaclass__ = ABCMeta |
| 58 | + |
| 59 | + def __init__( |
| 60 | + self, |
| 61 | + processor: "AbstractProcessor", |
| 62 | + memory: "AbstractMemory", |
| 63 | + cache_hierarchy: "AbstractCacheHierarchy", |
| 64 | + ) -> None: |
| 65 | + super(AbstractBoard, self).__init__() |
| 66 | + """ |
| 67 | + :param processor: The processor for this board. |
| 68 | + :param memory: The memory for this board. |
| 69 | + :param cache_hierarchy: The Cachie Hierarchy for this board. |
| 70 | + """ |
| 71 | + |
| 72 | + self.processor = processor |
| 73 | + self.memory = memory |
| 74 | + self.cache_hierarchy = cache_hierarchy |
| 75 | + |
| 76 | + def get_processor(self) -> "AbstractProcessor": |
| 77 | + """Get the processor connected to the board. |
| 78 | +
|
| 79 | + :returns: The processor. |
| 80 | + """ |
| 81 | + return self.processor |
| 82 | + |
| 83 | + def get_memory(self) -> "AbstractMemory": |
| 84 | + """Get the memory (RAM) connected to the board. |
| 85 | +
|
| 86 | + :returns: The memory system. |
| 87 | + """ |
| 88 | + return self.memory |
| 89 | + |
| 90 | + def get_cache_hierarchy(self) -> "AbstractCacheHierarchy": |
| 91 | + """Get the cache hierarchy connected to the board. |
| 92 | +
|
| 93 | + :returns: The cache hierarchy. |
| 94 | + """ |
| 95 | + return self.cache_hierarchy |
| 96 | + |
| 97 | + def get_cache_line_size(self) -> int: |
| 98 | + """Get the size of the cache line. |
| 99 | +
|
| 100 | + :returns: The size of the cache line size. |
| 101 | + """ |
| 102 | + return self.cache_line_size |
| 103 | + |
| 104 | + # Technically `get_dma_ports` returns a list. This list could be empty to |
| 105 | + # indicate the presense of dma ports. Though I quite like having this |
| 106 | + # boolean to quickly check a board. |
| 107 | + @abstractmethod |
| 108 | + def has_dma_ports(self) -> bool: |
| 109 | + """Determine whether the board has DMA ports or not. |
| 110 | +
|
| 111 | + :returns: True if the board has DMA ports, otherwise False. |
| 112 | + """ |
| 113 | + raise NotImplementedError |
| 114 | + |
| 115 | + @abstractmethod |
| 116 | + def get_dma_ports(self) -> List[Port]: |
| 117 | + """Get the board's Direct Memory Access ports. |
| 118 | + This abstract method must be implemented within the subclasses if they |
| 119 | + support DMA and/or full system simulation. |
| 120 | +
|
| 121 | + :returns: A List of the Direct Memory Access ports. |
| 122 | +
|
| 123 | + """ |
| 124 | + raise NotImplementedError |
| 125 | + |
| 126 | + @abstractmethod |
| 127 | + def has_io_bus(self) -> bool: |
| 128 | + """Determine whether the board has an IO bus or not. |
| 129 | +
|
| 130 | + :returns: True if the board has an IO bus, otherwise False. |
| 131 | + """ |
| 132 | + raise NotImplementedError |
| 133 | + |
| 134 | + @abstractmethod |
| 135 | + def get_io_bus(self) -> IOXBar: |
| 136 | + """Get the board's IO Bus. |
| 137 | + This abstract method must be implemented within the subclasses if they |
| 138 | + support DMA and/or full system simulation. |
| 139 | +
|
| 140 | + The I/O bus is a non-coherent bus (in the classic caches). On the CPU |
| 141 | + side, it accepts requests meant for I/O devices. On the memory side, it |
| 142 | + forwards these requests to the devices (e.g., the interrupt |
| 143 | + controllers on each core). |
| 144 | +
|
| 145 | + :returns: The I/O Bus. |
| 146 | + """ |
| 147 | + raise NotImplementedError |
| 148 | + |
| 149 | + @abstractmethod |
| 150 | + def get_clock_domain(self) -> ClockDomain: |
| 151 | + """Get the clock domain. |
| 152 | +
|
| 153 | + :returns: The clock domain. |
| 154 | + """ |
| 155 | + raise NotImplementedError |
| 156 | + |
| 157 | + @abstractmethod |
| 158 | + def connect_system_port(self, port: Port) -> None: |
| 159 | + raise NotImplementedError |
| 160 | + |
| 161 | + @abstractmethod |
| 162 | + def set_mem_mode(self, mem_mode: MemMode) -> None: |
| 163 | + """ |
| 164 | + Set the memory mode of the board. |
| 165 | +
|
| 166 | + :param mem_mode: The memory mode the board is to be set to. |
| 167 | + """ |
| 168 | + raise NotImplementedError |
| 169 | + |
| 170 | + @abstractmethod |
| 171 | + def connect_things(self) -> None: |
| 172 | + """Connects all the components to the board. |
| 173 | +
|
| 174 | + This should be called after the constructor. |
| 175 | +
|
| 176 | + When implementing this function, derived boards should use this to |
| 177 | + hook up the memory, process, and cache hierarchy as a *second* stage. |
| 178 | + You should use this function to connect things together when you need |
| 179 | + to know that everything has already been constructed. |
| 180 | + """ |
| 181 | + raise NotImplementedError |
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