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[vm] Add the RISC-V Zabha extension.
TEST=ci, local qemu Change-Id: Ie00951246c3b5eaa8ce8a038b60eea100b24fd6e Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/394664 Reviewed-by: Alexander Aprelev <[email protected]> Commit-Queue: Ryan Macnak <[email protected]>
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‎runtime/vm/compiler/assembler/assembler_riscv.cc‎

Lines changed: 162 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1711,6 +1711,168 @@ void MicroAssembler::czeronez(Register rd, Register rs1, Register rs2) {
17111711
EmitRType(CZERO, rs2, rs1, CZERONEZ, rd, OP);
17121712
}
17131713

1714+
void MicroAssembler::amoswapb(Register rd,
1715+
Register rs2,
1716+
Address addr,
1717+
std::memory_order order) {
1718+
ASSERT(addr.offset() == 0);
1719+
ASSERT(Supports(RV_Zabha));
1720+
EmitRType(AMOSWAP, order, rs2, addr.base(), WIDTH8, rd, AMO);
1721+
}
1722+
1723+
void MicroAssembler::amoaddb(Register rd,
1724+
Register rs2,
1725+
Address addr,
1726+
std::memory_order order) {
1727+
ASSERT(addr.offset() == 0);
1728+
ASSERT(Supports(RV_Zabha));
1729+
EmitRType(AMOADD, order, rs2, addr.base(), WIDTH8, rd, AMO);
1730+
}
1731+
1732+
void MicroAssembler::amoxorb(Register rd,
1733+
Register rs2,
1734+
Address addr,
1735+
std::memory_order order) {
1736+
ASSERT(addr.offset() == 0);
1737+
ASSERT(Supports(RV_Zabha));
1738+
EmitRType(AMOXOR, order, rs2, addr.base(), WIDTH8, rd, AMO);
1739+
}
1740+
1741+
void MicroAssembler::amoandb(Register rd,
1742+
Register rs2,
1743+
Address addr,
1744+
std::memory_order order) {
1745+
ASSERT(addr.offset() == 0);
1746+
ASSERT(Supports(RV_Zabha));
1747+
EmitRType(AMOAND, order, rs2, addr.base(), WIDTH8, rd, AMO);
1748+
}
1749+
1750+
void MicroAssembler::amoorb(Register rd,
1751+
Register rs2,
1752+
Address addr,
1753+
std::memory_order order) {
1754+
ASSERT(addr.offset() == 0);
1755+
ASSERT(Supports(RV_Zabha));
1756+
EmitRType(AMOOR, order, rs2, addr.base(), WIDTH8, rd, AMO);
1757+
}
1758+
1759+
void MicroAssembler::amominb(Register rd,
1760+
Register rs2,
1761+
Address addr,
1762+
std::memory_order order) {
1763+
ASSERT(addr.offset() == 0);
1764+
ASSERT(Supports(RV_Zabha));
1765+
EmitRType(AMOMIN, order, rs2, addr.base(), WIDTH8, rd, AMO);
1766+
}
1767+
1768+
void MicroAssembler::amomaxb(Register rd,
1769+
Register rs2,
1770+
Address addr,
1771+
std::memory_order order) {
1772+
ASSERT(addr.offset() == 0);
1773+
ASSERT(Supports(RV_Zabha));
1774+
EmitRType(AMOMAX, order, rs2, addr.base(), WIDTH8, rd, AMO);
1775+
}
1776+
1777+
void MicroAssembler::amominub(Register rd,
1778+
Register rs2,
1779+
Address addr,
1780+
std::memory_order order) {
1781+
ASSERT(addr.offset() == 0);
1782+
ASSERT(Supports(RV_Zabha));
1783+
EmitRType(AMOMINU, order, rs2, addr.base(), WIDTH8, rd, AMO);
1784+
}
1785+
1786+
void MicroAssembler::amomaxub(Register rd,
1787+
Register rs2,
1788+
Address addr,
1789+
std::memory_order order) {
1790+
ASSERT(addr.offset() == 0);
1791+
ASSERT(Supports(RV_Zabha));
1792+
EmitRType(AMOMAXU, order, rs2, addr.base(), WIDTH8, rd, AMO);
1793+
}
1794+
1795+
void MicroAssembler::amoswaph(Register rd,
1796+
Register rs2,
1797+
Address addr,
1798+
std::memory_order order) {
1799+
ASSERT(addr.offset() == 0);
1800+
ASSERT(Supports(RV_Zabha));
1801+
EmitRType(AMOSWAP, order, rs2, addr.base(), WIDTH16, rd, AMO);
1802+
}
1803+
1804+
void MicroAssembler::amoaddh(Register rd,
1805+
Register rs2,
1806+
Address addr,
1807+
std::memory_order order) {
1808+
ASSERT(addr.offset() == 0);
1809+
ASSERT(Supports(RV_Zabha));
1810+
EmitRType(AMOADD, order, rs2, addr.base(), WIDTH16, rd, AMO);
1811+
}
1812+
1813+
void MicroAssembler::amoxorh(Register rd,
1814+
Register rs2,
1815+
Address addr,
1816+
std::memory_order order) {
1817+
ASSERT(addr.offset() == 0);
1818+
ASSERT(Supports(RV_Zabha));
1819+
EmitRType(AMOXOR, order, rs2, addr.base(), WIDTH16, rd, AMO);
1820+
}
1821+
1822+
void MicroAssembler::amoandh(Register rd,
1823+
Register rs2,
1824+
Address addr,
1825+
std::memory_order order) {
1826+
ASSERT(addr.offset() == 0);
1827+
ASSERT(Supports(RV_Zabha));
1828+
EmitRType(AMOAND, order, rs2, addr.base(), WIDTH16, rd, AMO);
1829+
}
1830+
1831+
void MicroAssembler::amoorh(Register rd,
1832+
Register rs2,
1833+
Address addr,
1834+
std::memory_order order) {
1835+
ASSERT(addr.offset() == 0);
1836+
ASSERT(Supports(RV_Zabha));
1837+
EmitRType(AMOOR, order, rs2, addr.base(), WIDTH16, rd, AMO);
1838+
}
1839+
1840+
void MicroAssembler::amominh(Register rd,
1841+
Register rs2,
1842+
Address addr,
1843+
std::memory_order order) {
1844+
ASSERT(addr.offset() == 0);
1845+
ASSERT(Supports(RV_Zabha));
1846+
EmitRType(AMOMIN, order, rs2, addr.base(), WIDTH16, rd, AMO);
1847+
}
1848+
1849+
void MicroAssembler::amomaxh(Register rd,
1850+
Register rs2,
1851+
Address addr,
1852+
std::memory_order order) {
1853+
ASSERT(addr.offset() == 0);
1854+
ASSERT(Supports(RV_Zabha));
1855+
EmitRType(AMOMAX, order, rs2, addr.base(), WIDTH16, rd, AMO);
1856+
}
1857+
1858+
void MicroAssembler::amominuh(Register rd,
1859+
Register rs2,
1860+
Address addr,
1861+
std::memory_order order) {
1862+
ASSERT(addr.offset() == 0);
1863+
ASSERT(Supports(RV_Zabha));
1864+
EmitRType(AMOMINU, order, rs2, addr.base(), WIDTH16, rd, AMO);
1865+
}
1866+
1867+
void MicroAssembler::amomaxuh(Register rd,
1868+
Register rs2,
1869+
Address addr,
1870+
std::memory_order order) {
1871+
ASSERT(addr.offset() == 0);
1872+
ASSERT(Supports(RV_Zabha));
1873+
EmitRType(AMOMAXU, order, rs2, addr.base(), WIDTH16, rd, AMO);
1874+
}
1875+
17141876
void MicroAssembler::lb(Register rd, Address addr, std::memory_order order) {
17151877
ASSERT(addr.offset() == 0);
17161878
ASSERT((order == std::memory_order_acquire) ||

‎runtime/vm/compiler/assembler/assembler_riscv.h‎

Lines changed: 74 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -613,6 +613,80 @@ class MicroAssembler : public AssemblerBase {
613613
// rd := rs2 != 0 ? 0 : rs1
614614
void czeronez(Register rd, Register rs1, Register rs2);
615615

616+
// ==== Zabha: Byte and halfword AMOs ====
617+
void amoswapb(Register rd,
618+
Register rs2,
619+
Address addr,
620+
std::memory_order order = std::memory_order_relaxed);
621+
void amoaddb(Register rd,
622+
Register rs2,
623+
Address addr,
624+
std::memory_order order = std::memory_order_relaxed);
625+
void amoxorb(Register rd,
626+
Register rs2,
627+
Address addr,
628+
std::memory_order order = std::memory_order_relaxed);
629+
void amoandb(Register rd,
630+
Register rs2,
631+
Address addr,
632+
std::memory_order order = std::memory_order_relaxed);
633+
void amoorb(Register rd,
634+
Register rs2,
635+
Address addr,
636+
std::memory_order order = std::memory_order_relaxed);
637+
void amominb(Register rd,
638+
Register rs2,
639+
Address addr,
640+
std::memory_order order = std::memory_order_relaxed);
641+
void amomaxb(Register rd,
642+
Register rs2,
643+
Address addr,
644+
std::memory_order order = std::memory_order_relaxed);
645+
void amominub(Register rd,
646+
Register rs2,
647+
Address addr,
648+
std::memory_order order = std::memory_order_relaxed);
649+
void amomaxub(Register rd,
650+
Register rs2,
651+
Address addr,
652+
std::memory_order order = std::memory_order_relaxed);
653+
void amoswaph(Register rd,
654+
Register rs2,
655+
Address addr,
656+
std::memory_order order = std::memory_order_relaxed);
657+
void amoaddh(Register rd,
658+
Register rs2,
659+
Address addr,
660+
std::memory_order order = std::memory_order_relaxed);
661+
void amoxorh(Register rd,
662+
Register rs2,
663+
Address addr,
664+
std::memory_order order = std::memory_order_relaxed);
665+
void amoandh(Register rd,
666+
Register rs2,
667+
Address addr,
668+
std::memory_order order = std::memory_order_relaxed);
669+
void amoorh(Register rd,
670+
Register rs2,
671+
Address addr,
672+
std::memory_order order = std::memory_order_relaxed);
673+
void amominh(Register rd,
674+
Register rs2,
675+
Address addr,
676+
std::memory_order order = std::memory_order_relaxed);
677+
void amomaxh(Register rd,
678+
Register rs2,
679+
Address addr,
680+
std::memory_order order = std::memory_order_relaxed);
681+
void amominuh(Register rd,
682+
Register rs2,
683+
Address addr,
684+
std::memory_order order = std::memory_order_relaxed);
685+
void amomaxuh(Register rd,
686+
Register rs2,
687+
Address addr,
688+
std::memory_order order = std::memory_order_relaxed);
689+
616690
// ==== Zalasr: Load-acquire, store-release ====
617691
void lb(Register rd, Address addr, std::memory_order order);
618692
void lh(Register rd, Address addr, std::memory_order order);

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