[vm] Fix RISC-V ClobberAndCall to actually call.

TEST=ci
Change-Id: I6729c1b9c76094d88363cf0cb79e92288c3aa4eb
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/393600
Commit-Queue: Ryan Macnak <[email protected]>
Reviewed-by: Alexander Aprelev <[email protected]>

Author: rmacnak-google

runtime/bin/ffi_test/clobber_riscv32.S

@@ -9,7 +9,27 @@ ClobberAndCall:
 _ClobberAndCall:
 #endif
 
-li a0, 1
+/* Clobber all volatile registers and call the nullary function which is
+   passed in as the first argument. */
+
+addi sp, sp, -64
+sw ra, 60(sp)
+sw fp, 56(sp)
+addi fp, sp, 64
+
+sw s1, 40(sp)
+sw s2, 36(sp)
+sw s3, 32(sp)
+sw s4, 28(sp)
+sw s5, 24(sp)
+sw s6, 20(sp)
+sw s7, 16(sp)
+sw s8, 12(sp)
+sw s9, 8(sp)
+sw s10, 4(sp)
+sw s11, 0(sp)
+
+li ra, 1
 li a1, 1
 li a2, 1
 li a3, 1
@@ -24,4 +44,33 @@ li t3, 1
 li t4, 1
 li t5, 1
 li t6, 1
+li s1, 1
+li s2, 1
+li s3, 1
+li s4, 1
+li s5, 1
+li s6, 1
+li s7, 1
+li s8, 1
+li s9, 1
+li s10, 1
+li s11, 1
+
+jalr a0
+
+lw s11, 0(sp)
+lw s10, 4(sp)
+lw s9, 8(sp)
+lw s8, 12(sp)
+lw s7, 16(sp)
+lw s6, 20(sp)
+lw s5, 24(sp)
+lw s4, 28(sp)
+lw s3, 32(sp)
+lw s2, 36(sp)
+lw s1, 40(sp)
+
+lw fp, 56(sp)
+lw ra, 60(sp)
+addi sp, sp, 64
 ret

runtime/bin/ffi_test/clobber_riscv64.S

@@ -9,7 +9,27 @@ ClobberAndCall:
 _ClobberAndCall:
 #endif
 
-li a0, 1
+/* Clobber all volatile registers and call the nullary function which is
+   passed in as the first argument. */
+
+addi sp, sp, -112
+sd ra, 104(sp)
+sd fp, 96(sp)
+addi fp, sp, 112
+
+sd s1, 80(sp)
+sd s2, 72(sp)
+sd s3, 64(sp)
+sd s4, 56(sp)
+sd s5, 48(sp)
+sd s6, 40(sp)
+sd s7, 32(sp)
+sd s8, 24(sp)
+sd s9, 16(sp)
+sd s10, 8(sp)
+sd s11, 0(sp)
+
+li ra, 1
 li a1, 1
 li a2, 1
 li a3, 1
@@ -24,4 +44,33 @@ li t3, 1
 li t4, 1
 li t5, 1
 li t6, 1
+li s1, 1
+li s2, 1
+li s3, 1
+li s4, 1
+li s5, 1
+li s6, 1
+li s7, 1
+li s8, 1
+li s9, 1
+li s10, 1
+li s11, 1
+
+jalr a0
+
+ld s11, 0(sp)
+ld s10, 8(sp)
+ld s9, 16(sp)
+ld s8, 24(sp)
+ld s7, 32(sp)
+ld s6, 40(sp)
+ld s5, 48(sp)
+ld s4, 56(sp)
+ld s3, 64(sp)
+ld s2, 72(sp)
+ld s1, 80(sp)
+
+ld fp, 96(sp)
+ld ra, 104(sp)
+addi sp, sp, 112
 ret