[vm, compiler] Combine cset+sub into csetm for ARM64 IfThenElse.

TEST=ci
Change-Id: I64f70325ceca589ee93663f651a784c9c833ce36
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/464763
Reviewed-by: Alexander Markov <[email protected]>
Commit-Queue: Ryan Macnak <[email protected]>

Author: rmacnak-google

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -2528,7 +2528,7 @@ class Assembler : public AssemblerBase {
       return static_cast<Condition>((instr & kCondMask) >> kCondShift);
     }
     ASSERT(IsCompareAndBranch(instr));
-    return (instr & B24) ? EQ : NE;  // cbz : cbnz
+    return (instr & B24) != 0 ? EQ : NE;  // cbz : cbnz
   }
 
   int32_t EncodeImm19BranchCondition(Condition cond, int32_t instr) {
@@ -2542,7 +2542,7 @@ class Assembler : public AssemblerBase {
 
   Condition DecodeImm14BranchCondition(int32_t instr) {
     ASSERT(IsTestAndBranch(instr));
-    return (instr & B24) ? EQ : NE;  // tbz : tbnz
+    return (instr & B24) != 0 ? EQ : NE;  // tbz : tbnz
   }
 
   int32_t EncodeImm14BranchCondition(Condition cond, int32_t instr) {

runtime/vm/compiler/assembler/assembler_arm64_test.cc

@@ -412,21 +412,21 @@ ASSEMBLER_TEST_GENERATE(Overflow, assembler) {
   __ LoadImmediate(R3, 0x7FFFFFFFFFFFFFFF);
   __ adds(IP0, R2, Operand(R1));  // c_out = 1.
   __ adcs(IP0, R3, R0);           // c_in = 1, c_out = 1, v = 1.
-  __ csinc(R0, R0, R0, VS);       // R0 = v ? R0 : R0 + 1.
+  __ cset(R0, VS);                // R0 = v ? 1 : 0
   __ ret();
 }
 
 ASSEMBLER_TEST_RUN(Overflow, test) {
   typedef int64_t (*Int64Return)() DART_UNUSED;
-  EXPECT_EQ(0, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
+  EXPECT_EQ(1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
   EXPECT_DISASSEMBLY(
       "movz r0, #0x0\n"
       "movz r1, #0x1\n"
       "movn r2, #0x0\n"
       "mov r3, 0x7fffffffffffffff\n"
       "adds tmp, r2, r1\n"
       "adcs tmp, r3, r0\n"
-      "csinc r0, r0, r0, vs\n"
+      "cset r0, vs\n"
       "ret\n");
 }
 
@@ -481,21 +481,21 @@ ASSEMBLER_TEST_GENERATE(WordOverflow, assembler) {
   __ LoadImmediate(R3, 0x7FFFFFFF);
   __ addsw(IP0, R2, Operand(R1));  // c_out = 1.
   __ adcsw(IP0, R3, R0);           // c_in = 1, c_out = 1, v = 1.
-  __ csinc(R0, R0, R0, VS);        // R0 = v ? R0 : R0 + 1.
+  __ cset(R0, VS);                 // R0 = v ? 1 : 0
   __ ret();
 }
 
 ASSEMBLER_TEST_RUN(WordOverflow, test) {
   typedef int64_t (*Int64Return)() DART_UNUSED;
-  EXPECT_EQ(0, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
+  EXPECT_EQ(1, EXECUTE_TEST_CODE_INT64(Int64Return, test->entry()));
   EXPECT_DISASSEMBLY(
       "movz r0, #0x0\n"
       "movz r1, #0x1\n"
       "mov r2, 0xffffffff\n"
       "mov r3, 0x7fffffff\n"
       "addws tmp, r2, r1\n"
       "adcws tmp, r3, r0\n"
-      "csinc r0, r0, r0, vs\n"
+      "cset r0, vs\n"
       "ret\n");
 }
 
@@ -4165,7 +4165,7 @@ ASSEMBLER_TEST_RUN(CsincTrue, test) {
       "movz r1, #0x2a\n"
       "movz r2, #0x4d2\n"
       "cmp r1, r2\n"
-      "cinc r0, r2, ge\n"
+      "csinc r0, r2, r1, lt\n"
       "ret\n");
 }
 
@@ -4245,6 +4245,31 @@ ASSEMBLER_TEST_RUN(CsnegTrue, test) {
       "ret\n");
 }
 
+ASSEMBLER_TEST_GENERATE(CSelAliases, assembler) {
+  __ csel(R0, R1, R2, LT);
+  __ cset(R0, LT);
+  __ csetm(R0, LT);
+  __ csinc(R0, R1, R2, LT);
+  __ cinc(R0, R1, LT);
+  __ csinv(R0, R1, R2, LT);
+  __ cinv(R0, R1, LT);
+  __ csneg(R0, R1, R2, LT);
+  __ cneg(R0, R1, LT);
+}
+
+ASSEMBLER_TEST_RUN(CSelAliases, test) {
+  EXPECT_DISASSEMBLY(
+      "csel r0, r1, r2, lt\n"
+      "cset r0, lt\n"
+      "csetm r0, lt\n"
+      "csinc r0, r1, r2, lt\n"
+      "cinc r0, r1, lt\n"
+      "csinv r0, r1, r2, lt\n"
+      "cinv r0, r1, lt\n"
+      "csneg r0, r1, r2, lt\n"
+      "cneg r0, r1, lt\n");
+}
+
 ASSEMBLER_TEST_GENERATE(Ubfx, assembler) {
   __ LoadImmediate(R1, 0x819);
   __ LoadImmediate(R0, 0x5a5a5a5a);  // Overwritten.

runtime/vm/compiler/assembler/disassembler_arm64.cc

@@ -1307,13 +1307,21 @@ void ARM64Decoder::DecodeConditionalSelect(Instr* instr) {
     Format(instr, "csel'sf 'rd, 'rn, 'rm, 'cond");
   } else if ((instr->Bits(29, 2) == 0) && (instr->Bits(10, 2) == 1)) {
     if (non_select) {
-      Format(instr, "csinc'sf 'rd, 'rn, 'rm, 'cond");
+      if (instr->RnField() == 31 && instr->RmField() == 31) {
+        Format(instr, "cset'sf 'rd, 'condinverted");
+      } else {
+        Format(instr, "cinc'sf 'rd, 'rn, 'condinverted");
+      }
     } else {
-      Format(instr, "cinc'sf 'rd, 'rn, 'condinverted");
+      Format(instr, "csinc'sf 'rd, 'rn, 'rm, 'cond");
     }
   } else if ((instr->Bits(29, 2) == 2) && (instr->Bits(10, 2) == 0)) {
     if (non_select) {
-      Format(instr, "cinv'sf 'rd, 'rn, 'condinverted");
+      if (instr->RnField() == 31 && instr->RmField() == 31) {
+        Format(instr, "csetm'sf 'rd, 'condinverted");
+      } else {
+        Format(instr, "cinv'sf 'rd, 'rn, 'condinverted");
+      }
     } else {
       Format(instr, "csinv'sf 'rd, 'rn, 'rm, 'cond");
     }

runtime/vm/compiler/backend/il_arm64.cc

@@ -610,19 +610,17 @@ void IfThenElseInstr::EmitNativeCode(FlowGraphCompiler* compiler) {
       intptr_t temp = true_value;
       true_value = false_value;
       false_value = temp;
-    } else {
       true_condition = InvertCondition(true_condition);
     }
   }
 
-  __ cset(result, true_condition);
-
   if (is_power_of_two_kind) {
     const intptr_t shift =
         Utils::ShiftForPowerOfTwo(Utils::Maximum(true_value, false_value));
+    __ cset(result, true_condition);
     __ LslImmediate(result, result, shift + kSmiTagSize);
   } else {
-    __ sub(result, result, compiler::Operand(1));
+    __ csetm(result, true_condition);  // result = cond ? -1 : 0
     const int64_t val = Smi::RawValue(true_value) - Smi::RawValue(false_value);
     __ AndImmediate(result, result, val);
     if (false_value != 0) {

runtime/vm/constants_arm64.h

@@ -1614,7 +1614,8 @@ class Instr {
 
   static int64_t VFPExpandImm(uint8_t imm8) {
     const int64_t sign = static_cast<int64_t>((imm8 & 0x80) >> 7) << 63;
-    const int64_t hi_exp = static_cast<int64_t>(!((imm8 & 0x40) >> 6)) << 62;
+    const int64_t hi_exp = static_cast<int64_t>(((imm8 & 0x40) >> 6) == 0)
+                           << 62;
     const int64_t mid_exp = (((imm8 & 0x40) >> 6) == 0) ? 0 : (0xffLL << 54);
     const int64_t low_exp = static_cast<int64_t>((imm8 & 0x30) >> 4) << 52;
     const int64_t frac = static_cast<int64_t>(imm8 & 0x0f) << 48;