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[vm, compiler] Fix LR/SC assembler tests.
Compare 4242ff5. TEST=ci Change-Id: I3cc69504c380af02fa3869e73beef4112a60accb Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/393381 Commit-Queue: Ryan Macnak <[email protected]> Reviewed-by: Alexander Aprelev <[email protected]>
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2 files changed

+19
-5
lines changed

2 files changed

+19
-5
lines changed

runtime/vm/compiler/assembler/assembler_arm_test.cc

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -762,7 +762,7 @@ ASSEMBLER_TEST_GENERATE(Semaphore, assembler) {
762762
__ Bind(&retry);
763763
__ ldrex(R0, SP);
764764
__ strex(IP, R1, SP); // IP == 0, success
765-
__ tst(IP, Operand(0));
765+
__ cmp(IP, Operand(0));
766766
__ b(&retry, NE); // NE if context switch occurred between ldrex and strex.
767767
__ Pop(R0); // 42
768768
__ Ret();

runtime/vm/compiler/assembler/assembler_riscv_test.cc

Lines changed: 18 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2532,16 +2532,23 @@ ASSEMBLER_TEST_RUN(RemainderUnsignedWord, test) {
25322532

25332533
ASSEMBLER_TEST_GENERATE(LoadReserveStoreConditionalWord_Success, assembler) {
25342534
__ SetExtensions(RV_G);
2535+
2536+
Label retry;
2537+
__ Bind(&retry);
25352538
__ lrw(T0, Address(A0));
25362539
__ addi(T0, T0, 1);
2537-
__ scw(A0, T0, Address(A0));
2540+
__ scw(A1, T0, Address(A0));
2541+
__ bnez(A1, &retry);
2542+
__ mv(A0, A1);
25382543
__ ret();
25392544
}
25402545
ASSEMBLER_TEST_RUN(LoadReserveStoreConditionalWord_Success, test) {
25412546
EXPECT_DISASSEMBLY(
25422547
"100522af lr.w t0, (a0)\n"
25432548
"00128293 addi t0, t0, 1\n"
2544-
"1855252f sc.w a0, t0, (a0)\n"
2549+
"185525af sc.w a1, t0, (a0)\n"
2550+
"fe059ae3 bnez a1, -12\n"
2551+
"00058513 mv a0, a1\n"
25452552
"00008067 ret\n");
25462553

25472554
int32_t* value = reinterpret_cast<int32_t*>(malloc(sizeof(int32_t)));
@@ -2742,16 +2749,23 @@ ASSEMBLER_TEST_RUN(AmoMaxUnsignedWord, test) {
27422749
ASSEMBLER_TEST_GENERATE(LoadReserveStoreConditionalDoubleWord_Success,
27432750
assembler) {
27442751
__ SetExtensions(RV_G);
2752+
2753+
Label retry;
2754+
__ Bind(&retry);
27452755
__ lrd(T0, Address(A0));
27462756
__ addi(T0, T0, 1);
2747-
__ scd(A0, T0, Address(A0));
2757+
__ scd(A1, T0, Address(A0));
2758+
__ bnez(A1, &retry);
2759+
__ mv(A0, A1);
27482760
__ ret();
27492761
}
27502762
ASSEMBLER_TEST_RUN(LoadReserveStoreConditionalDoubleWord_Success, test) {
27512763
EXPECT_DISASSEMBLY(
27522764
"100532af lr.d t0, (a0)\n"
27532765
"00128293 addi t0, t0, 1\n"
2754-
"1855352f sc.d a0, t0, (a0)\n"
2766+
"185535af sc.d a1, t0, (a0)\n"
2767+
"fe059ae3 bnez a1, -12\n"
2768+
"00058513 mv a0, a1\n"
27552769
"00008067 ret\n");
27562770

27572771
int64_t* value = reinterpret_cast<int64_t*>(malloc(sizeof(int64_t)));

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