[vm, compiler] Use bit-manipulation extensions when targeting Android or Fuchsia RISC-V.

Use Zbb instructions when available for ClampedUint8List stores.
Use Zba instructions when available for IntConverter zero extensions.
Fix LslImmediate(kUnsignedFourBytes) when Zba is enabled.

TEST=locally switch to RV64GCB
Change-Id: If9fc0ac3fd2c5248785322f949e2003024e5152a
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/385640
Reviewed-by: Alexander Aprelev <[email protected]>
Commit-Queue: Ryan Macnak <[email protected]>

Author: rmacnak-google

runtime/vm/compiler/assembler/assembler_riscv.cc

@@ -2406,9 +2406,7 @@ void MicroAssembler::EmitJType(intptr_t imm, Register rd, Opcode opcode) {
 
 Assembler::Assembler(ObjectPoolBuilder* object_pool_builder,
                      intptr_t far_branch_level)
-    : MicroAssembler(object_pool_builder,
-                     far_branch_level,
-                     FLAG_use_compressed_instructions ? RV_GC : RV_G),
+    : MicroAssembler(object_pool_builder, far_branch_level, RV_baseline),
       constant_pool_allowed_(false) {
   generate_invoke_write_barrier_wrapper_ = [&](Register reg) {
     // Note this does not destroy RA.
@@ -2572,7 +2570,7 @@ void Assembler::ExtendValue(Register rd, Register rn, OperandSize sz) {
       return mv(rd, rn);
     case kUnsignedFourBytes:
       if (Supports(RV_Zba)) {
-        return adduw(rd, rn, ZR);
+        return zextw(rd, rn);
       }
       slli(rd, rn, XLEN - 32);
       return srli(rd, rn, XLEN - 32);
@@ -3311,13 +3309,12 @@ void Assembler::LslImmediate(Register rd,
     return slliw(rd, rn, shift);
   }
   if (sz == kUnsignedFourBytes) {
-    if (Supports(RV_Zba)) {
-      return slliuw(rd, rn, shift);
-    } else {
-      // Clear upper bits in addition to the shift.
-      slli(rd, rn, shift + (XLEN / 2));
-      return srli(rd, rn, XLEN / 2);
-    }
+    // Not slliuw even when available. That zero extends the input, not the
+    // output.
+
+    // Clear upper bits in addition to the shift.
+    slli(rd, rn, shift + (XLEN / 2));
+    return srli(rd, rn, XLEN / 2);
   }
 #endif
   slli(rd, rn, shift);

runtime/vm/compiler/assembler/assembler_riscv.h

@@ -69,6 +69,7 @@ class MicroAssembler : public AssemblerBase {
 #if defined(TESTING)
   void SetExtensions(ExtensionSet extensions) { extensions_ = extensions; }
 #endif
+  ExtensionSet extensions() const { return extensions_; }
   bool Supports(Extension extension) const {
     return extensions_.Includes(extension);
   }
@@ -562,6 +563,8 @@ class MicroAssembler : public AssemblerBase {
   void sh3adduw(Register rd, Register rs1, Register rs2);
   void slliuw(Register rd, Register rs1, intx_t imm);
 
+  void zextw(Register rd, Register rs) { adduw(rd, rs, ZR); }
+
   // ==== Zbb: Basic bit-manipulation ====
   void andn(Register rd, Register rs1, Register rs2);
   void orn(Register rd, Register rs1, Register rs2);