[vm,arm64] Fix AddImmediate in case of CSP

Use extended register variant of add instruction when Rd or Rn
register is CSP (SP). Also fix assertion which was incorrectly
testing that Rd cannot be CSP if extended register operand is used
(actually it cannot be ZR).

TEST=vm/cc/Assembler_Drop
Fixes #46433

Change-Id: I542dd7bc0661b3195fa466e43cd65998c1c4ac81
Reviewed-on: https://dart-review.googlesource.com/c/sdk/+/408141
Commit-Queue: Alexander Markov <[email protected]>
Reviewed-by: Ryan Macnak <[email protected]>

Author: alexmarkov

runtime/vm/compiler/assembler/assembler_arm64.cc

@@ -807,7 +807,11 @@ void Assembler::AddImmediate(Register dest,
     // TODO(zra): Try adding top 12 bits, then bottom 12 bits.
     ASSERT(rn != TMP2);
     LoadImmediate(TMP2, imm);
-    add(dest, rn, Operand(TMP2), sz);
+    if ((dest == CSP) || (rn == CSP)) {
+      add(dest, rn, Operand(TMP2, UXTX, 0), sz);
+    } else {
+      add(dest, rn, Operand(TMP2), sz);
+    }
   }
 }
 

runtime/vm/compiler/assembler/assembler_arm64.h

@@ -2342,7 +2342,7 @@ class Assembler : public AssemblerBase {
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     } else {
       ASSERT(o.type() == Operand::Extended);
-      ASSERT((rd != CSP) && (rn != ZR));
+      ASSERT((rd != ZR) && (rn != ZR));
       EmitAddSubShiftExtOp(subtract ? SUB : ADD, crd, crn, o, os, set_flags);
     }
   }