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[AArch64] Extend test coverage for v1i64 add/sub.sat. NFC
This cleans up the existing tests, removing duplicate tests and adding coverage for v1 types.
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-170
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8 files changed

+232
-170
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‎llvm/test/CodeGen/AArch64/sadd_sat.ll‎

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,6 @@
22
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

5-
declare i4 @llvm.sadd.sat.i4(i4, i4)
6-
declare i8 @llvm.sadd.sat.i8(i8, i8)
7-
declare i16 @llvm.sadd.sat.i16(i16, i16)
8-
declare i32 @llvm.sadd.sat.i32(i32, i32)
9-
declare i64 @llvm.sadd.sat.i64(i64, i64)
10-
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
11-
125
define i32 @func(i32 %x, i32 %y) nounwind {
136
; CHECK-SD-LABEL: func:
147
; CHECK-SD: // %bb.0:
@@ -135,12 +128,5 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
135128
%tmp = call i4 @llvm.sadd.sat.i4(i4 %x, i4 %y);
136129
ret i4 %tmp;
137130
}
138-
139-
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
140-
; CHECK-LABEL: vec:
141-
; CHECK: // %bb.0:
142-
; CHECK-NEXT: sqadd v0.4s, v0.4s, v1.4s
143-
; CHECK-NEXT: ret
144-
%tmp = call <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
145-
ret <4 x i32> %tmp;
146-
}
131+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
132+
; CHECK: {{.*}}

‎llvm/test/CodeGen/AArch64/sadd_sat_vec.ll‎

Lines changed: 60 additions & 31 deletions
Original file line numberDiff line numberDiff line change
@@ -5,37 +5,6 @@
55
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
66
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
77

8-
declare <1 x i8> @llvm.sadd.sat.v1i8(<1 x i8>, <1 x i8>)
9-
declare <2 x i8> @llvm.sadd.sat.v2i8(<2 x i8>, <2 x i8>)
10-
declare <4 x i8> @llvm.sadd.sat.v4i8(<4 x i8>, <4 x i8>)
11-
declare <8 x i8> @llvm.sadd.sat.v8i8(<8 x i8>, <8 x i8>)
12-
declare <12 x i8> @llvm.sadd.sat.v12i8(<12 x i8>, <12 x i8>)
13-
declare <16 x i8> @llvm.sadd.sat.v16i8(<16 x i8>, <16 x i8>)
14-
declare <32 x i8> @llvm.sadd.sat.v32i8(<32 x i8>, <32 x i8>)
15-
declare <64 x i8> @llvm.sadd.sat.v64i8(<64 x i8>, <64 x i8>)
16-
17-
declare <1 x i16> @llvm.sadd.sat.v1i16(<1 x i16>, <1 x i16>)
18-
declare <2 x i16> @llvm.sadd.sat.v2i16(<2 x i16>, <2 x i16>)
19-
declare <4 x i16> @llvm.sadd.sat.v4i16(<4 x i16>, <4 x i16>)
20-
declare <8 x i16> @llvm.sadd.sat.v8i16(<8 x i16>, <8 x i16>)
21-
declare <12 x i16> @llvm.sadd.sat.v12i16(<12 x i16>, <12 x i16>)
22-
declare <16 x i16> @llvm.sadd.sat.v16i16(<16 x i16>, <16 x i16>)
23-
declare <32 x i16> @llvm.sadd.sat.v32i16(<32 x i16>, <32 x i16>)
24-
25-
declare <16 x i1> @llvm.sadd.sat.v16i1(<16 x i1>, <16 x i1>)
26-
declare <16 x i4> @llvm.sadd.sat.v16i4(<16 x i4>, <16 x i4>)
27-
28-
declare <2 x i32> @llvm.sadd.sat.v2i32(<2 x i32>, <2 x i32>)
29-
declare <4 x i32> @llvm.sadd.sat.v4i32(<4 x i32>, <4 x i32>)
30-
declare <8 x i32> @llvm.sadd.sat.v8i32(<8 x i32>, <8 x i32>)
31-
declare <16 x i32> @llvm.sadd.sat.v16i32(<16 x i32>, <16 x i32>)
32-
declare <2 x i64> @llvm.sadd.sat.v2i64(<2 x i64>, <2 x i64>)
33-
declare <4 x i64> @llvm.sadd.sat.v4i64(<4 x i64>, <4 x i64>)
34-
declare <8 x i64> @llvm.sadd.sat.v8i64(<8 x i64>, <8 x i64>)
35-
36-
declare <4 x i24> @llvm.sadd.sat.v4i24(<4 x i24>, <4 x i24>)
37-
declare <2 x i128> @llvm.sadd.sat.v2i128(<2 x i128>, <2 x i128>)
38-
398
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
409
; CHECK-LABEL: v16i8:
4110
; CHECK: // %bb.0:
@@ -393,6 +362,34 @@ define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
393362
ret <16 x i1> %z
394363
}
395364

365+
define void @v1i32(ptr %px, ptr %py, ptr %pz) nounwind {
366+
; CHECK-SD-LABEL: v1i32:
367+
; CHECK-SD: // %bb.0:
368+
; CHECK-SD-NEXT: ldr s0, [x0]
369+
; CHECK-SD-NEXT: ldr s1, [x1]
370+
; CHECK-SD-NEXT: sqadd v0.2s, v0.2s, v1.2s
371+
; CHECK-SD-NEXT: str s0, [x2]
372+
; CHECK-SD-NEXT: ret
373+
;
374+
; CHECK-GI-LABEL: v1i32:
375+
; CHECK-GI: // %bb.0:
376+
; CHECK-GI-NEXT: ldr w8, [x0]
377+
; CHECK-GI-NEXT: ldr w9, [x1]
378+
; CHECK-GI-NEXT: adds w8, w8, w9
379+
; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x80000000
380+
; CHECK-GI-NEXT: cset w10, vs
381+
; CHECK-GI-NEXT: add w9, w9, w8, asr #31
382+
; CHECK-GI-NEXT: tst w10, #0x1
383+
; CHECK-GI-NEXT: csel w8, w9, w8, ne
384+
; CHECK-GI-NEXT: str w8, [x2]
385+
; CHECK-GI-NEXT: ret
386+
%x = load <1 x i32>, ptr %px
387+
%y = load <1 x i32>, ptr %py
388+
%z = call <1 x i32> @llvm.sadd.sat.v1i32(<1 x i32> %x, <1 x i32> %y)
389+
store <1 x i32> %z, ptr %pz
390+
ret void
391+
}
392+
396393
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
397394
; CHECK-LABEL: v2i32:
398395
; CHECK: // %bb.0:
@@ -447,6 +444,38 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
447444
ret <16 x i32> %z
448445
}
449446

447+
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
448+
; CHECK-SD-LABEL: v1i64:
449+
; CHECK-SD: // %bb.0:
450+
; CHECK-SD-NEXT: ldr x8, [x1]
451+
; CHECK-SD-NEXT: ldr x9, [x0]
452+
; CHECK-SD-NEXT: adds x8, x9, x8
453+
; CHECK-SD-NEXT: asr x9, x8, #63
454+
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
455+
; CHECK-SD-NEXT: csel x8, x9, x8, vs
456+
; CHECK-SD-NEXT: fmov d0, x8
457+
; CHECK-SD-NEXT: str d0, [x2]
458+
; CHECK-SD-NEXT: ret
459+
;
460+
; CHECK-GI-LABEL: v1i64:
461+
; CHECK-GI: // %bb.0:
462+
; CHECK-GI-NEXT: ldr x8, [x0]
463+
; CHECK-GI-NEXT: ldr x9, [x1]
464+
; CHECK-GI-NEXT: adds x8, x8, x9
465+
; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
466+
; CHECK-GI-NEXT: cset w10, vs
467+
; CHECK-GI-NEXT: add x9, x9, x8, asr #63
468+
; CHECK-GI-NEXT: tst w10, #0x1
469+
; CHECK-GI-NEXT: csel x8, x9, x8, ne
470+
; CHECK-GI-NEXT: str x8, [x2]
471+
; CHECK-GI-NEXT: ret
472+
%x = load <1 x i64>, ptr %px
473+
%y = load <1 x i64>, ptr %py
474+
%z = call <1 x i64> @llvm.sadd.sat.v1i64(<1 x i64> %x, <1 x i64> %y)
475+
store <1 x i64> %z, ptr %pz
476+
ret void
477+
}
478+
450479
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
451480
; CHECK-LABEL: v2i64:
452481
; CHECK: // %bb.0:

‎llvm/test/CodeGen/AArch64/ssub_sat.ll‎

Lines changed: 2 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -2,13 +2,6 @@
22
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

5-
declare i4 @llvm.ssub.sat.i4(i4, i4)
6-
declare i8 @llvm.ssub.sat.i8(i8, i8)
7-
declare i16 @llvm.ssub.sat.i16(i16, i16)
8-
declare i32 @llvm.ssub.sat.i32(i32, i32)
9-
declare i64 @llvm.ssub.sat.i64(i64, i64)
10-
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
11-
125
define i32 @func(i32 %x, i32 %y) nounwind {
136
; CHECK-SD-LABEL: func:
147
; CHECK-SD: // %bb.0:
@@ -135,12 +128,5 @@ define i4 @func3(i4 %x, i4 %y) nounwind {
135128
%tmp = call i4 @llvm.ssub.sat.i4(i4 %x, i4 %y);
136129
ret i4 %tmp;
137130
}
138-
139-
define <4 x i32> @vec(<4 x i32> %x, <4 x i32> %y) nounwind {
140-
; CHECK-LABEL: vec:
141-
; CHECK: // %bb.0:
142-
; CHECK-NEXT: sqsub v0.4s, v0.4s, v1.4s
143-
; CHECK-NEXT: ret
144-
%tmp = call <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32> %x, <4 x i32> %y);
145-
ret <4 x i32> %tmp;
146-
}
131+
;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
132+
; CHECK: {{.*}}

‎llvm/test/CodeGen/AArch64/ssub_sat_vec.ll‎

Lines changed: 60 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -5,38 +5,6 @@
55
; CHECK-GI: warning: Instruction selection used fallback path for v16i4
66
; CHECK-GI-NEXT: warning: Instruction selection used fallback path for v16i1
77

8-
declare <1 x i8> @llvm.ssub.sat.v1i8(<1 x i8>, <1 x i8>)
9-
declare <2 x i8> @llvm.ssub.sat.v2i8(<2 x i8>, <2 x i8>)
10-
declare <4 x i8> @llvm.ssub.sat.v4i8(<4 x i8>, <4 x i8>)
11-
declare <8 x i8> @llvm.ssub.sat.v8i8(<8 x i8>, <8 x i8>)
12-
declare <12 x i8> @llvm.ssub.sat.v12i8(<12 x i8>, <12 x i8>)
13-
declare <16 x i8> @llvm.ssub.sat.v16i8(<16 x i8>, <16 x i8>)
14-
declare <32 x i8> @llvm.ssub.sat.v32i8(<32 x i8>, <32 x i8>)
15-
declare <64 x i8> @llvm.ssub.sat.v64i8(<64 x i8>, <64 x i8>)
16-
17-
declare <1 x i16> @llvm.ssub.sat.v1i16(<1 x i16>, <1 x i16>)
18-
declare <2 x i16> @llvm.ssub.sat.v2i16(<2 x i16>, <2 x i16>)
19-
declare <4 x i16> @llvm.ssub.sat.v4i16(<4 x i16>, <4 x i16>)
20-
declare <8 x i16> @llvm.ssub.sat.v8i16(<8 x i16>, <8 x i16>)
21-
declare <12 x i16> @llvm.ssub.sat.v12i16(<12 x i16>, <12 x i16>)
22-
declare <16 x i16> @llvm.ssub.sat.v16i16(<16 x i16>, <16 x i16>)
23-
declare <32 x i16> @llvm.ssub.sat.v32i16(<32 x i16>, <32 x i16>)
24-
25-
declare <16 x i1> @llvm.ssub.sat.v16i1(<16 x i1>, <16 x i1>)
26-
declare <16 x i4> @llvm.ssub.sat.v16i4(<16 x i4>, <16 x i4>)
27-
28-
declare <2 x i32> @llvm.ssub.sat.v2i32(<2 x i32>, <2 x i32>)
29-
declare <4 x i32> @llvm.ssub.sat.v4i32(<4 x i32>, <4 x i32>)
30-
declare <8 x i32> @llvm.ssub.sat.v8i32(<8 x i32>, <8 x i32>)
31-
declare <16 x i32> @llvm.ssub.sat.v16i32(<16 x i32>, <16 x i32>)
32-
declare <2 x i64> @llvm.ssub.sat.v2i64(<2 x i64>, <2 x i64>)
33-
declare <4 x i64> @llvm.ssub.sat.v4i64(<4 x i64>, <4 x i64>)
34-
declare <8 x i64> @llvm.ssub.sat.v8i64(<8 x i64>, <8 x i64>)
35-
36-
declare <4 x i24> @llvm.ssub.sat.v4i24(<4 x i24>, <4 x i24>)
37-
declare <2 x i128> @llvm.ssub.sat.v2i128(<2 x i128>, <2 x i128>)
38-
39-
408
define <16 x i8> @v16i8(<16 x i8> %x, <16 x i8> %y) nounwind {
419
; CHECK-LABEL: v16i8:
4210
; CHECK: // %bb.0:
@@ -396,6 +364,34 @@ define <16 x i1> @v16i1(<16 x i1> %x, <16 x i1> %y) nounwind {
396364
ret <16 x i1> %z
397365
}
398366

367+
define void @v1i32(ptr %px, ptr %py, ptr %pz) nounwind {
368+
; CHECK-SD-LABEL: v1i32:
369+
; CHECK-SD: // %bb.0:
370+
; CHECK-SD-NEXT: ldr s0, [x0]
371+
; CHECK-SD-NEXT: ldr s1, [x1]
372+
; CHECK-SD-NEXT: sqsub v0.2s, v0.2s, v1.2s
373+
; CHECK-SD-NEXT: str s0, [x2]
374+
; CHECK-SD-NEXT: ret
375+
;
376+
; CHECK-GI-LABEL: v1i32:
377+
; CHECK-GI: // %bb.0:
378+
; CHECK-GI-NEXT: ldr w8, [x0]
379+
; CHECK-GI-NEXT: ldr w9, [x1]
380+
; CHECK-GI-NEXT: subs w8, w8, w9
381+
; CHECK-GI-NEXT: mov w9, #-2147483648 // =0x80000000
382+
; CHECK-GI-NEXT: cset w10, vs
383+
; CHECK-GI-NEXT: add w9, w9, w8, asr #31
384+
; CHECK-GI-NEXT: tst w10, #0x1
385+
; CHECK-GI-NEXT: csel w8, w9, w8, ne
386+
; CHECK-GI-NEXT: str w8, [x2]
387+
; CHECK-GI-NEXT: ret
388+
%x = load <1 x i32>, ptr %px
389+
%y = load <1 x i32>, ptr %py
390+
%z = call <1 x i32> @llvm.ssub.sat.v1i32(<1 x i32> %x, <1 x i32> %y)
391+
store <1 x i32> %z, ptr %pz
392+
ret void
393+
}
394+
399395
define <2 x i32> @v2i32(<2 x i32> %x, <2 x i32> %y) nounwind {
400396
; CHECK-LABEL: v2i32:
401397
; CHECK: // %bb.0:
@@ -450,6 +446,38 @@ define <16 x i32> @v16i32(<16 x i32> %x, <16 x i32> %y) nounwind {
450446
ret <16 x i32> %z
451447
}
452448

449+
define void @v1i64(ptr %px, ptr %py, ptr %pz) nounwind {
450+
; CHECK-SD-LABEL: v1i64:
451+
; CHECK-SD: // %bb.0:
452+
; CHECK-SD-NEXT: ldr x8, [x1]
453+
; CHECK-SD-NEXT: ldr x9, [x0]
454+
; CHECK-SD-NEXT: subs x8, x9, x8
455+
; CHECK-SD-NEXT: asr x9, x8, #63
456+
; CHECK-SD-NEXT: eor x9, x9, #0x8000000000000000
457+
; CHECK-SD-NEXT: csel x8, x9, x8, vs
458+
; CHECK-SD-NEXT: fmov d0, x8
459+
; CHECK-SD-NEXT: str d0, [x2]
460+
; CHECK-SD-NEXT: ret
461+
;
462+
; CHECK-GI-LABEL: v1i64:
463+
; CHECK-GI: // %bb.0:
464+
; CHECK-GI-NEXT: ldr x8, [x0]
465+
; CHECK-GI-NEXT: ldr x9, [x1]
466+
; CHECK-GI-NEXT: subs x8, x8, x9
467+
; CHECK-GI-NEXT: mov x9, #-9223372036854775808 // =0x8000000000000000
468+
; CHECK-GI-NEXT: cset w10, vs
469+
; CHECK-GI-NEXT: add x9, x9, x8, asr #63
470+
; CHECK-GI-NEXT: tst w10, #0x1
471+
; CHECK-GI-NEXT: csel x8, x9, x8, ne
472+
; CHECK-GI-NEXT: str x8, [x2]
473+
; CHECK-GI-NEXT: ret
474+
%x = load <1 x i64>, ptr %px
475+
%y = load <1 x i64>, ptr %py
476+
%z = call <1 x i64> @llvm.ssub.sat.v1i64(<1 x i64> %x, <1 x i64> %y)
477+
store <1 x i64> %z, ptr %pz
478+
ret void
479+
}
480+
453481
define <2 x i64> @v2i64(<2 x i64> %x, <2 x i64> %y) nounwind {
454482
; CHECK-LABEL: v2i64:
455483
; CHECK: // %bb.0:

‎llvm/test/CodeGen/AArch64/uadd_sat.ll‎

Lines changed: 0 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -2,12 +2,6 @@
22
; RUN: llc < %s -mtriple=aarch64-- | FileCheck %s --check-prefixes=CHECK,CHECK-SD
33
; RUN: llc < %s -mtriple=aarch64-- -global-isel | FileCheck %s --check-prefixes=CHECK,CHECK-GI
44

5-
declare i4 @llvm.uadd.sat.i4(i4, i4)
6-
declare i8 @llvm.uadd.sat.i8(i8, i8)
7-
declare i16 @llvm.uadd.sat.i16(i16, i16)
8-
declare i32 @llvm.uadd.sat.i32(i32, i32)
9-
declare i64 @llvm.uadd.sat.i64(i64, i64)
10-
115
define i32 @func(i32 %x, i32 %y) nounwind {
126
; CHECK-SD-LABEL: func:
137
; CHECK-SD: // %bb.0:

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