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19 | 19 | #include "AArch64Subtarget.h" |
20 | 20 | #include "MCTargetDesc/AArch64AddressingModes.h" |
21 | 21 | #include "Utils/AArch64BaseInfo.h" |
| 22 | +#include "Utils/AArch64SMEAttributes.h" |
22 | 23 | #include "llvm/ADT/APFloat.h" |
23 | 24 | #include "llvm/ADT/APInt.h" |
24 | 25 | #include "llvm/ADT/ArrayRef.h" |
@@ -10082,9 +10083,9 @@ SDValue AArch64TargetLowering::LowerGlobalTLSAddress(SDValue Op, |
10082 | 10083 | // Thus, it's only used for ptrauth references to extern_weak to avoid null |
10083 | 10084 | // checks. |
10084 | 10085 |
|
10085 | | -SDValue AArch64TargetLowering::LowerPtrAuthGlobalAddressStatically( |
| 10086 | +static SDValue LowerPtrAuthGlobalAddressStatically( |
10086 | 10087 | SDValue TGA, SDLoc DL, EVT VT, AArch64PACKey::ID KeyC, |
10087 | | - SDValue Discriminator, SDValue AddrDiscriminator, SelectionDAG &DAG) const { |
| 10088 | + SDValue Discriminator, SDValue AddrDiscriminator, SelectionDAG &DAG) { |
10088 | 10089 | const auto *TGN = cast<GlobalAddressSDNode>(TGA.getNode()); |
10089 | 10090 | assert(TGN->getGlobal()->hasExternalWeakLinkage()); |
10090 | 10091 |
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@@ -27574,6 +27575,22 @@ AArch64TargetLowering::getSafeStackPointerLocation(IRBuilderBase &IRB) const { |
27574 | 27575 | return TargetLowering::getSafeStackPointerLocation(IRB); |
27575 | 27576 | } |
27576 | 27577 |
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| 27578 | +/// If a physical register, this returns the register that receives the |
| 27579 | +/// exception address on entry to an EH pad. |
| 27580 | +Register AArch64TargetLowering::getExceptionPointerRegister( |
| 27581 | + const Constant *PersonalityFn) const { |
| 27582 | + // FIXME: This is a guess. Has this been defined yet? |
| 27583 | + return AArch64::X0; |
| 27584 | +} |
| 27585 | + |
| 27586 | +/// If a physical register, this returns the register that receives the |
| 27587 | +/// exception typeid on entry to a landing pad. |
| 27588 | +Register AArch64TargetLowering::getExceptionSelectorRegister( |
| 27589 | + const Constant *PersonalityFn) const { |
| 27590 | + // FIXME: This is a guess. Has this been defined yet? |
| 27591 | + return AArch64::X1; |
| 27592 | +} |
| 27593 | + |
27577 | 27594 | bool AArch64TargetLowering::isMaskAndCmp0FoldingBeneficial( |
27578 | 27595 | const Instruction &AndI) const { |
27579 | 27596 | // Only sink 'and' mask to cmp use block if it is masking a single bit, since |
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