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davemgreendavemgreen
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[ARM] Remove IR from mve vpt mir tests. NFC
As far as I can tell the llvm.arm.mve.vminnm.m intrinsic used in these tests was the pre-upstream name of llvm.arm.mve.min.predicated. The tests should not need IR sections, so remove them just relying on the MIR portions.
1 parent 9cb9b16 commit dc8311f

10 files changed

+23
-230
lines changed

‎llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-2-preds.mir‎

Lines changed: 2 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_2_preds(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p1, i16 zeroext %p2) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p1 to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%conv.i5 = zext i16 %p2 to i32
13-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %0, <4 x float> %b, i32 %conv.i5) #2
14-
ret <4 x float> %1
15-
}
16-
17-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
18-
19-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
20-
attributes #1 = { nounwind readnone }
21-
attributes #2 = { nounwind }
22-
23-
...
244
---
255
name: vpt_2_blocks_2_preds
266
alignment: 4
@@ -61,7 +41,7 @@ fixedStack: []
6141
stack: []
6242
constants: []
6343
body: |
64-
bb.0.entry:
44+
bb.0:
6545
liveins: $q0, $q1, $q2, $r0, $r1
6646
6747
; CHECK-LABEL: name: vpt_2_blocks_2_preds

‎llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-ctrl-flow.mir‎

Lines changed: 5 additions & 28 deletions
Original file line numberDiff line numberDiff line change
@@ -1,29 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_ctrl_flow(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13-
br label %bb2
14-
bb2:
15-
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
16-
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
17-
ret <4 x float> %3
18-
}
19-
20-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
21-
22-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
23-
attributes #1 = { nounwind readnone }
24-
attributes #2 = { nounwind }
25-
26-
...
274
---
285
name: vpt_2_blocks_ctrl_flow
296
alignment: 4
@@ -64,7 +41,7 @@ stack: []
6441
constants: []
6542
body: |
6643
; CHECK-LABEL: name: vpt_2_blocks_ctrl_flow
67-
; CHECK: bb.0.entry:
44+
; CHECK: bb.0:
6845
; CHECK: successors: %bb.1(0x80000000)
6946
; CHECK: liveins: $q0, $q1, $q2, $r0
7047
; CHECK: $vpr = VMSR_P0 killed $r0, 14 /* CC::al */, $noreg
@@ -74,23 +51,23 @@ body: |
7451
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
7552
; CHECK: renamable $q1 = nnan ninf nsz MVE_VMINNMf32 internal renamable $q3, internal renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
7653
; CHECK: }
77-
; CHECK: bb.1.bb2:
54+
; CHECK: bb.1:
7855
; CHECK: liveins: $q0, $q1, $q2, $q3, $vpr
7956
; CHECK: BUNDLE implicit-def dead $q3, implicit-def $q0, implicit killed $vpr, implicit killed $q1, implicit killed $q2, implicit killed $q3, implicit killed $q0 {
8057
; CHECK: MVE_VPST 4, implicit $vpr
8158
; CHECK: renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
8259
; CHECK: renamable $q0 = nnan ninf nsz MVE_VMINNMf32 internal killed renamable $q3, killed renamable $q2, 1, killed renamable $vpr, $noreg, killed renamable $q0
8360
; CHECK: }
8461
; CHECK: tBX_RET 14 /* CC::al */, $noreg, implicit $q0
85-
bb.0.entry:
62+
bb.0:
8663
liveins: $q0, $q1, $q2, $r0
8764
8865
$vpr = VMSR_P0 killed $r0, 14, $noreg
8966
$q3 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q3
9067
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3
9168
renamable $q1 = nnan ninf nsz MVE_VMINNMf32 renamable $q3, renamable $q3, 1, renamable $vpr, $noreg, undef renamable $q1
9269
93-
bb.1.bb2:
70+
bb.1:
9471
liveins: $q0, $q1, $q2, $q3, $vpr
9572
9673
renamable $q3 = nnan ninf nsz MVE_VMINNMf32 killed renamable $q1, renamable $q2, 1, renamable $vpr, $noreg, killed renamable $q3

‎llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks-non-consecutive-ins.mir‎

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks_non_consecutive_ins(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13-
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
14-
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
15-
ret <4 x float> %3
16-
}
17-
18-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
19-
20-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
21-
attributes #1 = { nounwind readnone }
22-
attributes #2 = { nounwind }
23-
24-
...
254
---
265
name: vpt_2_blocks_non_consecutive_ins
276
alignment: 4
@@ -61,7 +40,7 @@ fixedStack: []
6140
stack: []
6241
constants: []
6342
body: |
64-
bb.0.entry:
43+
bb.0:
6544
liveins: $q0, $q1, $q2, $r0
6645
6746

‎llvm/test/CodeGen/Thumb2/mve-vpt-2-blocks.mir‎

Lines changed: 2 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,28 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_2_blocks(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13-
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
14-
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
15-
%4 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %3, <4 x float> %b, i32 %conv.i) #2
16-
ret <4 x float> %4
17-
}
18-
19-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
20-
21-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
22-
attributes #1 = { nounwind readnone }
23-
attributes #2 = { nounwind }
24-
25-
...
264
---
275
name: vpt_2_blocks
286
alignment: 4
@@ -63,7 +41,7 @@ fixedStack: []
6341
stack: []
6442
constants: []
6543
body: |
66-
bb.0.entry:
44+
bb.0:
6745
liveins: $q0, $q1, $q2, $q3, $r0
6846
6947
; CHECK-LABEL: name: vpt_2_blocks

‎llvm/test/CodeGen/Thumb2/mve-vpt-3-blocks-kill-vpr.mir‎

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_3_blocks_kill_vpr(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13-
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
14-
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
15-
ret <4 x float> %3
16-
}
17-
18-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
19-
20-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
21-
attributes #1 = { nounwind readnone }
22-
attributes #2 = { nounwind }
23-
24-
...
254
---
265
name: vpt_3_blocks_kill_vpr
276
alignment: 4
@@ -61,7 +40,7 @@ fixedStack: []
6140
stack: []
6241
constants: []
6342
body: |
64-
bb.0.entry:
43+
bb.0:
6544
liveins: $q0, $q1, $q2, $r0
6645
6746
; CHECK-LABEL: name: vpt_3_blocks_kill_vpr

‎llvm/test/CodeGen/Thumb2/mve-vpt-block-1-ins.mir‎

Lines changed: 2 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -1,25 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_1_ins(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
ret <4 x float> %0
13-
}
14-
15-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
16-
17-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
18-
attributes #1 = { nounwind readnone }
19-
attributes #2 = { nounwind }
20-
21-
22-
...
234
---
245
name: vpt_block_1_ins
256
alignment: 4
@@ -59,7 +40,7 @@ fixedStack: []
5940
stack: []
6041
constants: []
6142
body: |
62-
bb.0.entry:
43+
bb.0:
6344
liveins: $q0, $q1, $q2, $r0
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; CHECK-LABEL: name: vpt_block_1_ins

‎llvm/test/CodeGen/Thumb2/mve-vpt-block-2-ins.mir‎

Lines changed: 2 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -1,26 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_2_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %0, <4 x float> %b, i32 %conv.i) #2
13-
ret <4 x float> %1
14-
}
15-
16-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
17-
18-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
19-
attributes #1 = { nounwind readnone }
20-
attributes #2 = { nounwind }
21-
22-
23-
...
244
---
255
name: vpt_block_2_ins
266
alignment: 4
@@ -61,7 +41,7 @@ fixedStack: []
6141
stack: []
6242
constants: []
6343
body: |
64-
bb.0.entry:
44+
bb.0:
6545
liveins: $q0, $q1, $q2, $q3, $r0
6646
6747
; CHECK-LABEL: name: vpt_block_2_ins

‎llvm/test/CodeGen/Thumb2/mve-vpt-block-4-ins.mir‎

Lines changed: 2 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,6 @@
11
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
2-
# RUN: llc -run-pass arm-mve-vpt %s -o - | FileCheck %s
2+
# RUN: llc -mtriple=thumbv8.1m.main-none-none-eabi -mattr=+mve.fp -run-pass arm-mve-vpt %s -o - | FileCheck %s
33

4-
--- |
5-
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
6-
target triple = "thumbv8.1m.main-none-none-eabi"
7-
8-
define hidden arm_aapcs_vfpcc <4 x float> @vpt_block_4_ins(<4 x float> %inactive1, <4 x float> %inactive2, <4 x float> %a, <4 x float> %b, i16 zeroext %p) local_unnamed_addr #0 {
9-
entry:
10-
%conv.i = zext i16 %p to i32
11-
%0 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %a, <4 x float> %b, i32 %conv.i) #2
12-
%1 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> undef, <4 x float> %0, <4 x float> %0, i32 %conv.i) #2
13-
%2 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive1, <4 x float> %1, <4 x float> %b, i32 %conv.i) #2
14-
%3 = tail call nnan ninf nsz <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float> %inactive2, <4 x float> %2, <4 x float> %b, i32 %conv.i) #2
15-
ret <4 x float> %3
16-
}
17-
18-
declare <4 x float> @llvm.arm.mve.vminnm.m.v4f32.v4f32.v4f32.v4f32.i32(<4 x float>, <4 x float>, <4 x float>, i32) #1
19-
20-
attributes #0 = { nounwind readnone "correctly-rounded-divide-sqrt-fp-math"="false" "denormal-fp-math"="preserve-sign" "disable-tail-calls"="false" "less-precise-fpmad"="false" "min-legal-vector-width"="128" "frame-pointer"="none" "no-infs-fp-math"="true" "no-jump-tables"="false" "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" "no-trapping-math"="true" "stack-protector-buffer-size"="8" "target-cpu"="generic" "target-features"="+armv8.1-m.main,+hwdiv,+mve.fp,+ras,+thumb-mode" "use-soft-float"="false" }
21-
attributes #1 = { nounwind readnone }
22-
attributes #2 = { nounwind }
23-
24-
...
254
---
265
name: vpt_block_4_ins
276
alignment: 4
@@ -62,7 +41,7 @@ fixedStack: []
6241
stack: []
6342
constants: []
6443
body: |
65-
bb.0.entry:
44+
bb.0:
6645
liveins: $q0, $q1, $q2, $q3, $r0
6746
6847
; CHECK-LABEL: name: vpt_block_4_ins

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