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[AArch64] Drop poison-generating flags in genSubAdd2SubSub combiner
A miscompilation issue has been addressed with improved handling. Fixes: llvm#88950.
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2 files changed

+38
-4
lines changed

2 files changed

+38
-4
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llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

Lines changed: 11 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -6924,19 +6924,26 @@ genSubAdd2SubSub(MachineFunction &MF, MachineRegisterInfo &MRI,
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assert((Opcode == AArch64::SUBWrr || Opcode == AArch64::SUBXrr) &&
69256925
"Unexpected instruction opcode.");
69266926

6927+
uint32_t Flags = Root.mergeFlagsWith(*AddMI);
6928+
Flags &= ~MachineInstr::NoSWrap;
6929+
Flags &= ~MachineInstr::NoUWrap;
6930+
69276931
MachineInstrBuilder MIB1 =
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BuildMI(MF, MIMetadata(Root), TII->get(Opcode), NewVR)
69296933
.addReg(RegA, getKillRegState(RegAIsKill))
6930-
.addReg(RegB, getKillRegState(RegBIsKill));
6934+
.addReg(RegB, getKillRegState(RegBIsKill))
6935+
.setMIFlags(Flags);
69316936
MachineInstrBuilder MIB2 =
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BuildMI(MF, MIMetadata(Root), TII->get(Opcode), ResultReg)
69336938
.addReg(NewVR, getKillRegState(true))
6934-
.addReg(RegC, getKillRegState(RegCIsKill));
6939+
.addReg(RegC, getKillRegState(RegCIsKill))
6940+
.setMIFlags(Flags);
69356941

69366942
InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
69376943
InsInstrs.push_back(MIB1);
69386944
InsInstrs.push_back(MIB2);
69396945
DelInstrs.push_back(AddMI);
6946+
DelInstrs.push_back(&Root);
69406947
}
69416948

69426949
/// When getMachineCombinerPatterns() finds potential patterns,
@@ -6966,13 +6973,13 @@ void AArch64InstrInfo::genAlternativeCodeSequence(
69666973
// ==> (A - B) - C
69676974
genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 1,
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InstrIdxForVirtReg);
6969-
break;
6976+
return;
69706977
case AArch64MachineCombinerPattern::SUBADD_OP2:
69716978
// A - (B + C)
69726979
// ==> (A - C) - B
69736980
genSubAdd2SubSub(MF, MRI, TII, Root, InsInstrs, DelInstrs, 2,
69746981
InstrIdxForVirtReg);
6975-
break;
6982+
return;
69766983
case AArch64MachineCombinerPattern::MULADDW_OP1:
69776984
case AArch64MachineCombinerPattern::MULADDX_OP1:
69786985
// MUL I=A,B,0

llvm/test/CodeGen/AArch64/machine-combiner-subadd2.mir

Lines changed: 27 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -237,3 +237,30 @@ body: |
237237
RET_ReallyLR implicit $w0
238238
239239
...
240+
---
241+
# Drop nowrap flags in SUB
242+
243+
# CHECK-LABEL: name: test8
244+
# CHECK: %7:gpr64 = SUBXrr %1, %0
245+
# CHECK-NEXT: %4:gpr64common = SUBXrr killed %7, killed %2
246+
247+
name: test8
248+
registers:
249+
- { id: 0, class: gpr64 }
250+
- { id: 1, class: gpr64 }
251+
- { id: 2, class: gpr64common }
252+
- { id: 3, class: gpr64 }
253+
- { id: 4, class: gpr64common }
254+
- { id: 5, class: gpr64 }
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body: |
256+
bb.0:
257+
%1:gpr64 = COPY $x1
258+
%0:gpr64 = COPY $x0
259+
%2:gpr64common = ORRXri %0:gpr64, 4096
260+
%3:gpr64 = ADDXrr killed %2:gpr64common, %0:gpr64
261+
%4:gpr64common = nsw SUBSXrr %1:gpr64, killed %3:gpr64, implicit-def dead $nzcv
262+
%5:gpr64 = SUBSXri %4:gpr64common, 0, 0, implicit-def $nzcv
263+
$x0 = COPY %5:gpr64
264+
RET_ReallyLR implicit $x0
265+
266+
...

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