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[SelectionDAG] Add SDNode::user_begin() and use it in some places (llvm#120509)
Most of these are just places that want the first user and aren't iterating over the whole list. While there I changed some use_size() == 1 to hasOneUse() which is more efficient. This is part of an effort to rename use_iterator to user_iterator and provide a use_iterator that dereferences to SDUse&. This patch helps reduce the diff on later patches.
1 parent 4ca4287 commit bd261ec

16 files changed

+92
-88
lines changed

‎llvm/include/llvm/CodeGen/SelectionDAGNodes.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -844,6 +844,11 @@ END_TWO_BYTE_PACK()
844844

845845
static use_iterator use_end() { return use_iterator(nullptr); }
846846

847+
/// Provide iteration support to walk over all users of an SDNode.
848+
/// For now, this should only be used to get a pointer to the first user.
849+
/// FIXME: Rename use_iterator to user_iterator. Add user_end().
850+
use_iterator user_begin() const { return use_iterator(UseList); }
851+
847852
// Dereferencing use_iterator returns the user SDNode* making it closer to a
848853
// user_iterator thus this function is called users() to reflect that.
849854
// FIXME: Rename to user_iterator and introduce a use_iterator that returns

‎llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

Lines changed: 19 additions & 19 deletions
Original file line numberDiff line numberDiff line change
@@ -2136,8 +2136,8 @@ SDValue DAGCombiner::visitTokenFactor(SDNode *N) {
21362136
// If the sole user is a token factor, we should make sure we have a
21372137
// chance to merge them together. This prevents TF chains from inhibiting
21382138
// optimizations.
2139-
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::TokenFactor)
2140-
AddToWorklist(*(N->use_begin()));
2139+
if (N->hasOneUse() && N->user_begin()->getOpcode() == ISD::TokenFactor)
2140+
AddToWorklist(*(N->user_begin()));
21412141

21422142
SmallVector<SDNode *, 8> TFs; // List of token factors to visit.
21432143
SmallVector<SDValue, 8> Ops; // Ops for replacing token factor.
@@ -10906,15 +10906,15 @@ SDValue DAGCombiner::visitSRL(SDNode *N) {
1090610906
// which we plan to do. This workaround can be removed once the DAG is
1090710907
// processed in topological order.
1090810908
if (N->hasOneUse()) {
10909-
SDNode *Use = *N->use_begin();
10909+
SDNode *User = *N->user_begin();
1091010910

1091110911
// Look pass the truncate.
10912-
if (Use->getOpcode() == ISD::TRUNCATE && Use->hasOneUse())
10913-
Use = *Use->use_begin();
10912+
if (User->getOpcode() == ISD::TRUNCATE && User->hasOneUse())
10913+
User = *User->user_begin();
1091410914

10915-
if (Use->getOpcode() == ISD::BRCOND || Use->getOpcode() == ISD::AND ||
10916-
Use->getOpcode() == ISD::OR || Use->getOpcode() == ISD::XOR)
10917-
AddToWorklist(Use);
10915+
if (User->getOpcode() == ISD::BRCOND || User->getOpcode() == ISD::AND ||
10916+
User->getOpcode() == ISD::OR || User->getOpcode() == ISD::XOR)
10917+
AddToWorklist(User);
1091810918
}
1091910919

1092010920
// Try to transform this shift into a multiply-high if
@@ -12917,7 +12917,7 @@ SDValue DAGCombiner::visitSETCC(SDNode *N) {
1291712917
// also lend itself to numerous combines and, as a result, it is desired
1291812918
// we keep the argument to a brcond as a setcc as much as possible.
1291912919
bool PreferSetCC =
12920-
N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BRCOND;
12920+
N->hasOneUse() && N->user_begin()->getOpcode() == ISD::BRCOND;
1292112921

1292212922
ISD::CondCode Cond = cast<CondCodeSDNode>(N->getOperand(2))->get();
1292312923
EVT VT = N->getValueType(0);
@@ -14825,7 +14825,7 @@ SDValue DAGCombiner::reduceLoadWidth(SDNode *N) {
1482514825

1482614826
// If the SRL is only used by a masking AND, we may be able to adjust
1482714827
// the ExtVT to make the AND redundant.
14828-
SDNode *Mask = *(SRL->use_begin());
14828+
SDNode *Mask = *(SRL->user_begin());
1482914829
if (SRL.hasOneUse() && Mask->getOpcode() == ISD::AND &&
1483014830
isa<ConstantSDNode>(Mask->getOperand(1))) {
1483114831
unsigned Offset, ActiveBits;
@@ -15364,7 +15364,7 @@ SDValue DAGCombiner::visitTRUNCATE(SDNode *N) {
1536415364
}
1536515365

1536615366
// If this is anyext(trunc), don't fold it, allow ourselves to be folded.
15367-
if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ANY_EXTEND))
15367+
if (N->hasOneUse() && (N->user_begin()->getOpcode() == ISD::ANY_EXTEND))
1536815368
return SDValue();
1536915369

1537015370
// Fold extract-and-trunc into a narrow extract. For example:
@@ -18370,7 +18370,7 @@ SDValue DAGCombiner::visitFP_EXTEND(SDNode *N) {
1837018370
return FoldedVOp;
1837118371

1837218372
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
18373-
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::FP_ROUND)
18373+
if (N->hasOneUse() && N->user_begin()->getOpcode() == ISD::FP_ROUND)
1837418374
return SDValue();
1837518375

1837618376
// fold (fp_extend c1fp) -> c1fp
@@ -19847,17 +19847,17 @@ struct LoadedSlice {
1984719847
bool canMergeExpensiveCrossRegisterBankCopy() const {
1984819848
if (!Inst || !Inst->hasOneUse())
1984919849
return false;
19850-
SDNode *Use = *Inst->use_begin();
19851-
if (Use->getOpcode() != ISD::BITCAST)
19850+
SDNode *User = *Inst->user_begin();
19851+
if (User->getOpcode() != ISD::BITCAST)
1985219852
return false;
1985319853
assert(DAG && "Missing context");
1985419854
const TargetLowering &TLI = DAG->getTargetLoweringInfo();
19855-
EVT ResVT = Use->getValueType(0);
19855+
EVT ResVT = User->getValueType(0);
1985619856
const TargetRegisterClass *ResRC =
19857-
TLI.getRegClassFor(ResVT.getSimpleVT(), Use->isDivergent());
19857+
TLI.getRegClassFor(ResVT.getSimpleVT(), User->isDivergent());
1985819858
const TargetRegisterClass *ArgRC =
19859-
TLI.getRegClassFor(Use->getOperand(0).getValueType().getSimpleVT(),
19860-
Use->getOperand(0)->isDivergent());
19859+
TLI.getRegClassFor(User->getOperand(0).getValueType().getSimpleVT(),
19860+
User->getOperand(0)->isDivergent());
1986119861
if (ArgRC == ResRC || !TLI.isOperationLegal(ISD::LOAD, ResVT))
1986219862
return false;
1986319863

@@ -20069,7 +20069,7 @@ bool DAGCombiner::SliceUpLoad(SDNode *N) {
2006920069
if (User->getOpcode() == ISD::SRL && User->hasOneUse() &&
2007020070
isa<ConstantSDNode>(User->getOperand(1))) {
2007120071
Shift = User->getConstantOperandVal(1);
20072-
User = *User->use_begin();
20072+
User = *User->user_begin();
2007320073
}
2007420074

2007520075
// At this point, User is a Truncate, iff we encountered, trunc or

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -18109,9 +18109,9 @@ bool AArch64TargetLowering::shouldFoldConstantShiftPairToMask(
1810918109
if (N->getOpcode() == ISD::SHL && N->hasOneUse()) {
1811018110
if (auto C2 = dyn_cast<ConstantSDNode>(N->getOperand(1))) {
1811118111
unsigned ShlAmt = C2->getZExtValue();
18112-
if (auto ShouldADD = *N->use_begin();
18112+
if (auto ShouldADD = *N->user_begin();
1811318113
ShouldADD->getOpcode() == ISD::ADD && ShouldADD->hasOneUse()) {
18114-
if (auto ShouldLOAD = dyn_cast<LoadSDNode>(*ShouldADD->use_begin())) {
18114+
if (auto ShouldLOAD = dyn_cast<LoadSDNode>(*ShouldADD->user_begin())) {
1811518115
unsigned ByteVT = ShouldLOAD->getMemoryVT().getSizeInBits() / 8;
1811618116
if ((1ULL << ShlAmt) == ByteVT &&
1811718117
isIndexedLoadLegal(ISD::PRE_INC, ShouldLOAD->getMemoryVT()))
@@ -18902,8 +18902,8 @@ static SDValue performMulCombine(SDNode *N, SelectionDAG &DAG,
1890218902
return SDValue();
1890318903
// Conservatively do not lower to shift+add+shift if the mul might be
1890418904
// folded into madd or msub.
18905-
if (N->hasOneUse() && (N->use_begin()->getOpcode() == ISD::ADD ||
18906-
N->use_begin()->getOpcode() == ISD::SUB))
18905+
if (N->hasOneUse() && (N->user_begin()->getOpcode() == ISD::ADD ||
18906+
N->user_begin()->getOpcode() == ISD::SUB))
1890718907
return SDValue();
1890818908
}
1890918909
// Use ShiftedConstValue instead of ConstValue to support both shift+add/sub
@@ -21803,7 +21803,7 @@ static SDValue tryCombineWhileLo(SDNode *N,
2180321803
if (HalfSize < 2)
2180421804
return SDValue();
2180521805

21806-
auto It = N->use_begin();
21806+
auto It = N->user_begin();
2180721807
SDNode *Lo = *It++;
2180821808
SDNode *Hi = *It;
2180921809

@@ -23402,7 +23402,7 @@ static SDValue performPostLD1Combine(SDNode *N,
2340223402
// TODO: This could be expanded to more operations if they reliably use the
2340323403
// index variants.
2340423404
if (N->hasOneUse()) {
23405-
unsigned UseOpc = N->use_begin()->getOpcode();
23405+
unsigned UseOpc = N->user_begin()->getOpcode();
2340623406
if (UseOpc == ISD::FMUL || UseOpc == ISD::FMA)
2340723407
return SDValue();
2340823408
}
@@ -24755,7 +24755,7 @@ static SDValue tryToWidenSetCCOperands(SDNode *Op, SelectionDAG &DAG) {
2475524755

2475624756
// Make sure that all uses of Op are VSELECTs with result matching types where
2475724757
// the result type has a larger element type than the SetCC operand.
24758-
SDNode *FirstUse = *Op->use_begin();
24758+
SDNode *FirstUse = *Op->user_begin();
2475924759
if (FirstUse->getOpcode() != ISD::VSELECT)
2476024760
return SDValue();
2476124761
EVT UseMVT = FirstUse->getValueType(0);
@@ -25905,7 +25905,7 @@ static SDValue performFPExtendCombine(SDNode *N, SelectionDAG &DAG,
2590525905
EVT VT = N->getValueType(0);
2590625906

2590725907
// If this is fp_round(fpextend), don't fold it, allow ourselves to be folded.
25908-
if (N->hasOneUse() && N->use_begin()->getOpcode() == ISD::FP_ROUND)
25908+
if (N->hasOneUse() && N->user_begin()->getOpcode() == ISD::FP_ROUND)
2590925909
return SDValue();
2591025910

2591125911
auto hasValidElementTypeForFPExtLoad = [](EVT VT) {
@@ -26072,7 +26072,7 @@ static SDValue tryCombineMULLWithUZP1(SDNode *N,
2607226072

2607326073
// Check ExtractLow's user.
2607426074
if (HasFoundMULLow) {
26075-
SDNode *ExtractLowUser = *ExtractLow.getNode()->use_begin();
26075+
SDNode *ExtractLowUser = *ExtractLow.getNode()->user_begin();
2607626076
if (ExtractLowUser->getOpcode() != N->getOpcode()) {
2607726077
HasFoundMULLow = false;
2607826078
} else {
@@ -26549,7 +26549,7 @@ bool AArch64TargetLowering::isUsedByReturnOnly(SDNode *N,
2654926549
return false;
2655026550

2655126551
SDValue TCChain = Chain;
26552-
SDNode *Copy = *N->use_begin();
26552+
SDNode *Copy = *N->user_begin();
2655326553
if (Copy->getOpcode() == ISD::CopyToReg) {
2655426554
// If the copy has a glue operand, we conservatively assume it isn't safe to
2655526555
// perform a tail call.

‎llvm/lib/Target/AMDGPU/AMDGPUISelLowering.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1088,9 +1088,9 @@ bool AMDGPUTargetLowering::isDesirableToCommuteWithShift(
10881088
return true;
10891089

10901090
// If only user is a i32 right-shift, then don't destroy a BFE pattern.
1091-
if (N->getValueType(0) == MVT::i32 && N->use_size() == 1 &&
1092-
(N->use_begin()->getOpcode() == ISD::SRA ||
1093-
N->use_begin()->getOpcode() == ISD::SRL))
1091+
if (N->getValueType(0) == MVT::i32 && N->hasOneUse() &&
1092+
(N->user_begin()->getOpcode() == ISD::SRA ||
1093+
N->user_begin()->getOpcode() == ISD::SRL))
10941094
return false;
10951095

10961096
// Don't destroy or(shl(load_zext(),c), load_zext()) patterns.

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -16896,7 +16896,7 @@ bool SITargetLowering::isReassocProfitable(SelectionDAG &DAG, SDValue N0,
1689616896
// Check if we have a good chance to form the memory access pattern with the
1689716897
// base and offset
1689816898
return (DAG.isBaseWithConstantOffset(N0) &&
16899-
hasMemSDNodeUser(*N0->use_begin()));
16899+
hasMemSDNodeUser(*N0->user_begin()));
1690016900
}
1690116901

1690216902
bool SITargetLowering::isReassocProfitable(MachineRegisterInfo &MRI,

‎llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -505,14 +505,14 @@ bool ARMDAGToDAGISel::hasNoVMLxHazardUse(SDNode *N) const {
505505
if (!N->hasOneUse())
506506
return false;
507507

508-
SDNode *Use = *N->use_begin();
509-
if (Use->getOpcode() == ISD::CopyToReg)
508+
SDNode *User = *N->user_begin();
509+
if (User->getOpcode() == ISD::CopyToReg)
510510
return true;
511-
if (Use->isMachineOpcode()) {
511+
if (User->isMachineOpcode()) {
512512
const ARMBaseInstrInfo *TII = static_cast<const ARMBaseInstrInfo *>(
513513
CurDAG->getSubtarget().getInstrInfo());
514514

515-
const MCInstrDesc &MCID = TII->get(Use->getMachineOpcode());
515+
const MCInstrDesc &MCID = TII->get(User->getMachineOpcode());
516516
if (MCID.mayStore())
517517
return true;
518518
unsigned Opcode = MCID.getOpcode();

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 14 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -3456,7 +3456,7 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
34563456
return false;
34573457

34583458
SDValue TCChain = Chain;
3459-
SDNode *Copy = *N->use_begin();
3459+
SDNode *Copy = *N->user_begin();
34603460
if (Copy->getOpcode() == ISD::CopyToReg) {
34613461
// If the copy has a glue operand, we conservatively assume it isn't safe to
34623462
// perform a tail call.
@@ -3494,7 +3494,7 @@ bool ARMTargetLowering::isUsedByReturnOnly(SDNode *N, SDValue &Chain) const {
34943494
// f32 returned in a single GPR.
34953495
if (!Copy->hasOneUse())
34963496
return false;
3497-
Copy = *Copy->use_begin();
3497+
Copy = *Copy->user_begin();
34983498
if (Copy->getOpcode() != ISD::CopyToReg || !Copy->hasNUsesOfValue(1, 0))
34993499
return false;
35003500
// If the copy has a glue operand, we conservatively assume it isn't safe to
@@ -15356,7 +15356,7 @@ PerformARMBUILD_VECTORCombine(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
1535615356
assert(EltVT == MVT::f32 && "Unexpected type!");
1535715357

1535815358
// Check 1.2.
15359-
SDNode *Use = *N->use_begin();
15359+
SDNode *Use = *N->user_begin();
1536015360
if (Use->getOpcode() != ISD::BITCAST ||
1536115361
Use->getValueType(0).isFloatingPoint())
1536215362
return SDValue();
@@ -15561,9 +15561,8 @@ PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
1556115561
!isa<ConstantSDNode>(Ext.getOperand(1)) ||
1556215562
Ext.getConstantOperandVal(1) % 2 != 0)
1556315563
return SDValue();
15564-
if (Ext->use_size() == 1 &&
15565-
(Ext->use_begin()->getOpcode() == ISD::SINT_TO_FP ||
15566-
Ext->use_begin()->getOpcode() == ISD::UINT_TO_FP))
15564+
if (Ext->hasOneUse() && (Ext->user_begin()->getOpcode() == ISD::SINT_TO_FP ||
15565+
Ext->user_begin()->getOpcode() == ISD::UINT_TO_FP))
1556715566
return SDValue();
1556815567

1556915568
SDValue Op0 = Ext.getOperand(0);
@@ -15587,11 +15586,11 @@ PerformExtractEltToVMOVRRD(SDNode *N, TargetLowering::DAGCombinerInfo &DCI) {
1558715586
// lanes.
1558815587
SDValue OtherExt(*OtherIt, 0);
1558915588
if (OtherExt.getValueType() != MVT::i32) {
15590-
if (OtherExt->use_size() != 1 ||
15591-
OtherExt->use_begin()->getOpcode() != ISD::BITCAST ||
15592-
OtherExt->use_begin()->getValueType(0) != MVT::i32)
15589+
if (!OtherExt->hasOneUse() ||
15590+
OtherExt->user_begin()->getOpcode() != ISD::BITCAST ||
15591+
OtherExt->user_begin()->getValueType(0) != MVT::i32)
1559315592
return SDValue();
15594-
OtherExt = SDValue(*OtherExt->use_begin(), 0);
15593+
OtherExt = SDValue(*OtherExt->user_begin(), 0);
1559515594
}
1559615595

1559715596
// Convert the type to a f64 and extract with a VMOVRRD.
@@ -18326,9 +18325,9 @@ static SDValue PerformHWLoopCombine(SDNode *N,
1832618325
SelectionDAG &DAG = DCI.DAG;
1832718326
SDValue Elements = Int.getOperand(2);
1832818327
unsigned IntOp = Int->getConstantOperandVal(1);
18329-
assert((N->hasOneUse() && N->use_begin()->getOpcode() == ISD::BR)
18330-
&& "expected single br user");
18331-
SDNode *Br = *N->use_begin();
18328+
assert((N->hasOneUse() && N->user_begin()->getOpcode() == ISD::BR) &&
18329+
"expected single br user");
18330+
SDNode *Br = *N->user_begin();
1833218331
SDValue OtherTarget = Br->getOperand(1);
1833318332

1833418333
// Update the unconditional branch to branch to the given Dest.
@@ -19330,10 +19329,10 @@ bool ARMTargetLowering::isVectorLoadExtDesirable(SDValue ExtVal) const {
1933019329
// If there's more than one user instruction, the loadext is desirable no
1933119330
// matter what. There can be two uses by the same instruction.
1933219331
if (ExtVal->use_empty() ||
19333-
!ExtVal->use_begin()->isOnlyUserOf(ExtVal.getNode()))
19332+
!ExtVal->user_begin()->isOnlyUserOf(ExtVal.getNode()))
1933419333
return true;
1933519334

19336-
SDNode *U = *ExtVal->use_begin();
19335+
SDNode *U = *ExtVal->user_begin();
1933719336
if ((U->getOpcode() == ISD::ADD || U->getOpcode() == ISD::SUB ||
1933819337
U->getOpcode() == ISD::SHL || U->getOpcode() == ARMISD::VSHLIMM))
1933919338
return false;

‎llvm/lib/Target/Hexagon/HexagonISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1097,7 +1097,7 @@ static bool isMemOPCandidate(SDNode *I, SDNode *U) {
10971097
SDValue S1 = U->getOperand(1);
10981098
SDValue SY = (S0.getNode() == I) ? S1 : S0;
10991099

1100-
SDNode *UUse = *U->use_begin();
1100+
SDNode *UUse = *U->user_begin();
11011101
if (UUse->getNumValues() != 1)
11021102
return false;
11031103

@@ -2431,7 +2431,7 @@ void HexagonDAGToDAGISel::rebalanceAddressTrees() {
24312431
Worklist.push_back(N->getOperand(1).getNode());
24322432

24332433
// Not a root if it has only one use and same opcode as its parent
2434-
if (N->hasOneUse() && Opcode == N->use_begin()->getOpcode())
2434+
if (N->hasOneUse() && Opcode == N->user_begin()->getOpcode())
24352435
continue;
24362436

24372437
// This root node has already been processed

‎llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5340,7 +5340,7 @@ bool LoongArchTargetLowering::isUsedByReturnOnly(SDNode *N,
53405340
if (!N->hasNUsesOfValue(1, 0))
53415341
return false;
53425342

5343-
SDNode *Copy = *N->use_begin();
5343+
SDNode *Copy = *N->user_begin();
53445344
if (Copy->getOpcode() != ISD::CopyToReg)
53455345
return false;
53465346

‎llvm/lib/Target/PowerPC/PPCISelDAGToDAG.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -6610,7 +6610,7 @@ void PPCDAGToDAGISel::foldBoolExts(SDValue &Res, SDNode *&N) {
66106610
SDValue ConstFalse = CurDAG->getConstant(0, dl, VT);
66116611

66126612
do {
6613-
SDNode *User = *N->use_begin();
6613+
SDNode *User = *N->user_begin();
66146614
if (User->getNumOperands() != 2)
66156615
break;
66166616

@@ -7564,7 +7564,7 @@ static void reduceVSXSwap(SDNode *N, SelectionDAG *DAG) {
75647564
while (V->isMachineOpcode() &&
75657565
V->getMachineOpcode() == TargetOpcode::COPY_TO_REGCLASS) {
75667566
// All values in the chain should have single use.
7567-
if (V->use_empty() || !V->use_begin()->isOnlyUserOf(V.getNode()))
7567+
if (V->use_empty() || !V->user_begin()->isOnlyUserOf(V.getNode()))
75687568
return SDValue();
75697569
V = V->getOperand(0);
75707570
}

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