Merge pull request #146 from davidgiven/sixbit

Switch to a simplified encoding with a six-bit timer.

Author: davidgiven

FluxEngine.cydsn/CortexM3/ARM_GCC_541/Release/FluxEngine.hex

@@ -39,20 +39,6 @@
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-<Hidden v="False" />
-</CyGuid_31768f72-0253-412b-af77-e7dba74d1330>
-<build_action v="SOURCE_C;;;;" />
-<PropertyDeltas />
-</CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b>
-<CyGuid_8b8ab257-35d3-4473-b57b-36315200b38b type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtFileSerialize" version="3" xml_contents_version="1">
-<CyGuid_31768f72-0253-412b-af77-e7dba74d1330 type_name="CyDesigner.Common.ProjMgmt.Model.CyPrjMgmtItemSerialize" version="2" name="crunch.h" persistent="..\lib\common\crunch.h">
-<Hidden v="False" />
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-<build_action v="HEADER;;;;" />
-<PropertyDeltas />
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 </dependencies>
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FluxEngine.cydsn/FluxEngine.cyprj

@@ -19,90 +19,78 @@ module Sampler (
 
 //`#start body` -- edit after this line, do not edit this line
 
-localparam STATE_RESET = 0;
-localparam STATE_WAITING = 1;
-localparam STATE_OPCODE = 2;
+localparam STATE_WAITING = 0;
+localparam STATE_OPCODE = 1;
 
-reg [1:0] state;
-reg [6:0] counter;
+reg [0:0] state;
+reg [5:0] counter;
 
 reg oldsampleclock;
-wire sampleclocked;
-assign sampleclocked = !oldsampleclock && sampleclock;
-
 reg oldindex;
-wire indexed;
-assign indexed = !oldindex && index;
-
-wire rdataed;
 reg oldrdata;
-assign rdataed = !oldrdata && rdata;
+
+reg sampleclocked;
+reg indexed;
+reg rdataed;
 
 assign req = (state == STATE_OPCODE);
 
 always @(posedge clock)
 begin
     if (reset)
     begin
-        state <= STATE_RESET;
+        state <= STATE_WAITING;
         opcode <= 0;
+        sampleclocked <= 0;
+        indexed <= 0;
+        rdataed <= 0;
         oldsampleclock <= 0;
         oldindex <= 0;
         oldrdata <= 0;
         counter <= 0;
     end
     else
+    begin
+        /* Remember positive egdes for sampleclock, index and rdata. */
+        
+        if (sampleclock && !oldsampleclock)
+            sampleclocked <= 1;
+        oldsampleclock <= sampleclock;
+        
+        if (index && !oldindex)
+            indexed <= 1;
+        oldindex <= index;
+        
+        if (rdata && !oldrdata)
+            rdataed <= 1;
+        oldrdata <= rdata;
+        
         case (state)
-            STATE_RESET:
-                state <= STATE_WAITING;
-            
             STATE_WAITING:
             begin
-                /* If something has happened, emit any necessary interval byte. */
-                if ((rdataed || indexed) && (counter != 0))
+                if (sampleclocked)
                 begin
-                    opcode <= {0, counter};
-                    state <= STATE_OPCODE;
-                end
-                else if (indexed)
-                begin
-                    oldindex <= 1;
-                    opcode <= 8'h81;
-                    state <= STATE_OPCODE;
-                end
-                else if (rdataed)
-                begin
-                    oldrdata <= 1;
-                    opcode <= 8'h80;
-                    state <= STATE_OPCODE;
-                end
-                else if (sampleclocked)
-                begin
-                    oldsampleclock <= 1;
-                    if (counter == 7'h7f)
+                    if (rdataed || indexed || (counter == 6'h3f))
                     begin
-                        opcode <= {0, counter};
+                        opcode <= {rdataed, indexed, counter};
+                        rdataed <= 0;
+                        indexed <= 0;
+                        counter <= 0;
                         state <= STATE_OPCODE;
                     end
-                    counter <= counter + 1;
+                    else
+                        counter <= counter + 1;
+                        
+                    sampleclocked <= 0;
                 end
-                
-                /* Reset state once we've done the thing. */
-                
-                if (oldrdata && !rdata)
-                    oldrdata <= 0;
-                if (oldindex && !index)
-                    oldindex <= 0;
-                if (oldsampleclock && !sampleclock)
-                    oldsampleclock <= 0;
             end
 
-            STATE_OPCODE: /* opcode or interval byte sent here */
+            STATE_OPCODE: /* opcode sent here */
             begin
                 state <= STATE_WAITING;
-                counter <= 0;
             end
         endcase
+    end
 end
 
 //`#end` -- edit above this line, do not edit this line

FluxEngine.cydsn/Sampler/Sampler.v

@@ -19,19 +19,15 @@ module Sequencer (
 //`#start body` -- edit after this line, do not edit this line
 
 localparam STATE_LOAD = 0;
-localparam STATE_WAITING = 1;
-localparam STATE_PULSING = 2;
-localparam STATE_INDEXING = 3;
+localparam STATE_WRITING = 1;
 
-localparam OPCODE_PULSE = 8'h80;
-localparam OPCODE_INDEX = 8'h81;
-
-reg [1:0] state;
-reg [6:0] countdown;
+reg state;
+reg [5:0] countdown;
+reg pulsepending;
 
 assign req = (!reset && (state == STATE_LOAD));
-assign wdata = (state == STATE_PULSING);
-assign debug_state = state;
+assign wdata = (!reset && (state == STATE_WRITING) && (countdown == 0) && pulsepending);
+assign debug_state = 0;
 
 reg olddataclock;
 wire dataclocked;
@@ -52,49 +48,39 @@ begin
     begin
         state <= STATE_LOAD;
         countdown <= 0;
+        pulsepending <= 0;
+        oldsampleclock <= 0;
     end
     else
     begin
         if (!oldsampleclock && sampleclock)
             sampleclocked <= 1;
         oldsampleclock <= sampleclock;
-        
+            
         case (state)
             STATE_LOAD:
-                /* Wait for a posedge on dataclocked, indicating an opcode has
+            begin
+                /* A posedge on dataclocked indicates that another opcode has
                  * arrived. */
                 if (dataclocked)
-                    case (opcode)
-                        OPCODE_PULSE:
-                            state <= STATE_PULSING;
-                        
-                        OPCODE_INDEX:
-                            state <= STATE_INDEXING;
-                        
-                        default:
-                        begin
-                            countdown <= opcode[6:0];
-                            state <= STATE_WAITING;
-                        end
-                    endcase
+                begin
+                    pulsepending <= opcode[7];
+                    countdown <= opcode[5:0];
+                    state <= STATE_WRITING;
+                end
+            end
 
-            STATE_WAITING:
+            STATE_WRITING:
+            begin
                 if (sampleclocked)
                 begin
-                    sampleclocked <= 0;
-                    countdown <= countdown - 1;
-                    /* Nasty fudge factor here to account for one to two
-                     * sample ticks lost per pulse. */
-                    if (countdown <= 2)
+                    if (countdown == 0)
                         state <= STATE_LOAD;
+                    else
+                        countdown <= countdown - 1;
+                    sampleclocked <= 0;
                 end
-            
-            STATE_PULSING:
-                state <= STATE_LOAD;
-            
-            STATE_INDEXING:
-                if (indexed)
-                    state <= STATE_LOAD;
+            end
         endcase
     end
 end