This document contains errata for RISC-V System-on-Chip Design published by Elsevier.
Please contribute by making a pull request to modify this document on GitHub. Sort the errata by page number. Keep the correction as succinct as possible.
Sample Errata
| Page | Location | Error | Correction | Contributor |
|---|---|---|---|---|
| 42 | Fig 1.42 | foobar | FooBar | Ben Bitdiddle, Claremont, CA |