papi_events.csv

#
# Every CPU automatically has PAPI_TOT_CYC and PAPI_TOT_INS added
#
# Processor identifier and additional flags.
# The processor identifier *can not* contain any comma characters as these
# characters serve to delimit fields.
#
CPU,AMD64 (K7)
CPU,amd64_k7
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
CPU,AMD64
CPU,AMD64 (unknown model)
CPU,AMD64 (K8 RevB)
CPU,AMD64 (K8 RevC)
CPU,AMD64 (K8 RevD)
CPU,AMD64 (K8 RevE)
CPU,AMD64 (K8 RevF)
CPU,AMD64 (K8 RevG)
CPU,amd64_k8_revb
CPU,amd64_k8_revc
CPU,amd64_k8_revd
CPU,amd64_k8_reve
CPU,amd64_k8_revf
CPU,amd64_k8_revg
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2
#    This definition give an accurate count of the instructions retired through the FP unit
#    It counts just about everything except MMX and 3DNow instructions
#    Unfortunately, it also counts loads and stores. Therefore the count will be uniformly
#    high, but proportional to the work done.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2
#/*  This definition is speculative but gives good answers on our simple test cases
#    It overcounts FP operations, sometimes by A LOT, but doesn't count loads and stores
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,'Counts speculative adds and multiplies. Variable and higher than theoretical.'
#
CPU,AMD64 FPU RETIRED
#
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,NOTE,"Counts all retired floating point operations, including data movement. Precise, and proportional to work done, but much higher than theoretical."
#
CPU,AMD64 FPU SPECULATIVE
#
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY:OPS_ADD,NOTE,"Counts speculative adds and multiplies. Variable and higher than theoretical."
#
CPU,AMD64 FPU SSE_SP
#
PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE,NOTE,"Counts retired ops corrected for data motion. Optimized for single precision; lower than theoretical."
#
CPU,AMD64 FPU SSE_DP
#
PRESET,PAPI_FP_OPS,DERIVED_SUB,RETIRED_MMX_AND_FP_INSTRUCTIONS:X87:SCALAR_SSE_AND_SSE2:PACKED_SSE_AND_SSE2,DISPATCHED_FPU:OPS_STORE_PIPE_LOAD_OPS,NOTE,"Counts retired ops corrected for data motion. Optimized for double precision; lower than theoretical."
#

########################
# AMD64                #
########################

CPU,AMD64 (Barcelona)
CPU,AMD64 (Barcelona RevB)
CPU,AMD64 (Barcelona RevC)
CPU,AMD64 (Family 10h RevB Barcelona)
CPU,AMD64 (Family 10h RevC Shanghai)
CPU,AMD64 (Family 10h RevD Istanbul)
CPU,AMD64 (Family 10h RevE)
CPU,amd64_fam10h_barcelona
CPU,amd64_fam10h_shanghai
CPU,amd64_fam10h_istanbul
CPU,amd64_fam11h_turion
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# no L3_ preset definitions for multi-cores with shared L3 cache,
# as long as L3 events are automatically shadowed from core- to chip-space
# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:PACKED_SSE_AND_SSE2
#
#    An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions
#    John McCalpin reports that OP_TYPE expands packed operation counts appropriately.
#    Therefore, it is included in FP_OPS, but not in FP_INS.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,"Also includes subtract instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"


########################
# AMD64 fam12h llano   #
########################

CPU,amd64_fam12h_llano
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# no L3_ preset definitions for multi-cores with shared L3 cache,
# as long as L3 events are automatically shadowed from core- to chip-space
# PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_AND_L2_DTLB_MISS:ALL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1_DTLB_AND_L2_DTLB_MISS:ALL,L1_ITLB_MISS_AND_L2_ITLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FML_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_MULTIPLY
PRESET,PAPI_FAD_INS,NOT_DERIVED,DISPATCHED_FPU:OPS_ADD
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_AND_FP_INSTRUCTIONS:SSE_AND_SSE2
#
#    An analysis by Bill Homer of Cray indicates accurate counts over a range of conditions
#    John McCalpin reports that OP_TYPE expands packed operation counts appropriately.
#    Therefore, it is included in FP_OPS, but not in FP_INS.
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:OP_TYPE
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:OP_TYPE,NOTE,"Also includes subtract instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS:OP_TYPE,NOTE,"Counts both divide and square root instructions"


#########################
# AMD Fam14h Bobcat     #
#########################

#
CPU,amd64_fam14h_bobcat
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,L1_ITLB_MISS_AND_L2_ITLB_MISS
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_NO_FPU_OPS_RETIRED
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_FLOATING_POINT_INSTRUCTIONS:ALL
PRESET,PAPI_FP_OPS,NOT_DERIVED,DISPATCHED_FPU:ANY
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:ALL
PRESET,PAPI_VEC_SP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_VEC_DP,NOT_DERIVED,RETIRED_SSE_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS
#
CPU,AMD64 (Family 15h RevB)
CPU,amd64_fam15h_interlagos
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2:INSTRUCTIONS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS
PRESET,PAPI_L2_ICH,NOT_DERIVED,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L2_DCA,NOT_DERIVED,REQUESTS_TO_L2:DATA
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_DCH,DERIVED_SUB,REQUESTS_TO_L2:DATA,L2_CACHE_MISS:DATA
PRESET,PAPI_L2_TCA,NOT_DERIVED,REQUESTS_TO_L2:ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS:INSTRUCTIONS:DATA
PRESET,PAPI_L2_TCH,DERIVED_SUB,REQUESTS_TO_L2:INSTRUCTIONS:DATA,L2_CACHE_MISS:ALL
#
# not implemented: PRESET,PAPI_L3_TCR,NOT_DERIVED,READ_REQUEST_TO_L3_CACHE:ALL
# not implemented: PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_CACHE_MISSES:ALL
# not implemented: PRESET,PAPI_L3_TCH,DERIVED_SUB,READ_REQUEST_TO_L3_CACHE:ALL,L3_CACHE_MISSES:ALL
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_DATA:2M_DATA:1GB_DATA
PRESET,PAPI_TLB_IM,NOT_DERIVED,UNIFIED_TLB_MISS:4K_INST:2M_INST:1G_INST
PRESET,PAPI_TLB_TL,NOT_DERIVED,UNIFIED_TLB_MISS:ALL
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,DECODER_EMPTY
PRESET,PAPI_RES_STL,NOT_DERIVED,DISPATCH_STALLS
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_FPU_IDL,NOT_DERIVED,CYCLES_FPU_EMPTY
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_OPS:ALL
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:ALL
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS:SINGLE_MUL_ADD_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_OPS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS:DOUBLE_MUL_ADD_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,"Also includes multiply-add instructions"
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS:SINGLE_MUL_ADD_OPS:DOUBLE_MUL_ADD_OPS,NOTE,"Also includes subtract and multiply-add instructions"
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_OPS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
#
#
CPU,amd64_fam16h
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_ICH,DERIVED_SUB,INSTRUCTION_CACHE_FETCHES,INSTRUCTION_CACHE_REFILLS_FROM_SYSTEM,INSTRUCTION_CACHE_REFILLS_FROM_L2
PRESET,PAPI_L1_ICM,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_ICR,NOT_DERIVED,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_CACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
#PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_CACHE_ACCESSES,DATA_CACHE_MISSES:DC_MISS_STREAMING_STORE
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,INSTRUCTION_CACHE_MISSES,DATA_CACHE_MISSES
# Only have 3 slots???
#PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|+|N2|-|N3|-|,DATA_CACHE_ACCESSES,INSTRUCTION_CACHE_FETCHES,DATA_CACHE_MISSES,INSTRUCTION_CACHE_MISSES
#
PRESET,PAPI_L2_ICA,NOT_DERIVED,INSTRUCTION_CACHE_MISSES
#
# Note, need access to special L2 uncore events
#	to get L2 related events
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,DTLB_MISS,ITLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_FETCH_STALL
PRESET,PAPI_HW_INT,NOT_DERIVED,INTERRUPTS_TAKEN
#
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:SINGLE_MUL_OPS:SINGLE_DIV_OPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DOUBLE_ADD_SUB_OPS:DOUBLE_MUL_OPS:DOUBLE_DIV_OPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_MUL_OPS:DOUBLE_MUL_OPS
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_ADD_SUB_OPS:DOUBLE_ADD_SUB_OPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SINGLE_DIV_OPS:DOUBLE_DIV_OPS,NOTE,"Counts both divide and square root instructions"
#
#
CPU,amd64_fam17h
CPU,amd64_fam17h_zen1
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
PRESET,PAPI_L1_ICM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
# Same event code, confusing name?
#PRESET,PAPI_L1_DCM,NOT_DERIVED,MAB_ALLOCATION_BY_PIPE
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_CACHE_ACCESSES
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
#
# Note, need access to special L2 uncore events
#	to get L2 related events
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:IF1G:IF2M:IF4K
#
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
# Note, the processor supports various kinds of mispredictions
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
#
PRESET,PAPI_STL_ICY,NOT_DERIVED,INSTRUCTION_PIPE_STALL:IC_STALL_ANY
#
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS:DP_MULT_FLOPS:DP_ADD_SUB_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS:SP_MULT_FLOPS:SP_ADD_SUB_FLOPS
PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:SP_MULT_FLOPS:SP_MULT_ADD_FLOPS:SP_DIV_FLOPS
PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:DP_ADD_SUB_FLOPS:DP_MULT_FLOPS:DP_MULT_ADD_FLOPS:DP_DIV_FLOPS
#
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_MULT_FLOPS:DP_MULT_FLOPS
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_ADD_SUB_FLOPS:DP_ADD_SUB_FLOPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,"Counts both divide and square root instructions"
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_OPERATIONS:SP_DIV_FLOPS:DP_DIV_FLOPS,NOTE,"Counts both divide and square root instructions"
# Events discovered via CAT
PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C
PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L
PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_L_HIT_X
#
#
CPU,amd64_fam17h_zen2
# Events copied from zen1 that also exist on zen2
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:IF1G:IF2M:IF4K
PRESET,PAPI_BR_TKN,NOT_DERIVED,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
# Events discovered via CAT
PRESET,PAPI_L1_DCA,NOT_DERIVED,perf::PERF_COUNT_HW_CACHE_L1D:ACCESS
PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C
PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L
PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_L_HIT_X
#
PRESET,PAPI_L1_ICM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
#
PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S
# New FLOP event on zen2
# PPR (under section 2.1.15.3. --
# https://www.amd.com/system/files/TechDocs/54945_3.03_ppr_ZP_B2_pub.zip)
# explains that FLOP events require MergeEvent support, which was included 
# in the 5.6 kernel. 
# Hence, a kernel version 5.6 or greater is required.
# NOTE: without the MergeEvent support in the kernel, there is no guarantee
# that this SSE/AVX FLOP event produces any useful data whatsoever.  
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
# Since FP_OPS counts both single- and double-prec operations
# correctly, we don't need to confuse the user with additional
# DP_OPS and SP_OPS events. So, I'm taking them out.  
#PRESET,PAPI_DP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
#PRESET,PAPI_SP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
#
# Floating-point instructions (including non-numeric floating-point instructions,
# e.g. Move or Merge Scalar Double-Precision Floating-Point values)
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR
# Since FP_INS counts both single- and double-prec instuctions
# correctly, we don't need to confuse the user with additional
# VEC_DP and VEC_SP events. So, I'm taking them out.  
#PRESET,PAPI_VEC_DP,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR
#PRESET,PAPI_VEC_SP,NOT_DERIVED,RETIRED_MMX_FP_INSTRUCTIONS:SSE_INSTR:MMX_INSTR:X87_INSTR
#
#
CPU,amd64_fam19h_zen3
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_CN,NOT_DERIVED,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_UCN,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,DERIVED_POSTFIX,N0|N1|-|N2|+|,RETIRED_TAKEN_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_NTK,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
PRESET,PAPI_TLB_DM,NOT_DERIVED,	L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:COALESCED4K:IF1G:IF2M:IF4K
PRESET,PAPI_L1_DCA,NOT_DERIVED,LS_DISPATCH:LD_ST_DISPATCH:STORE_DISPATCH:LD_DISPATCH
PRESET,PAPI_L1_DCM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X
PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C
PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X
PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X
PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S
# RETIRED_SSE_AVX_FLOPS requires MergeEvent support.
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
PRESET,PAPI_FP_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
PRESET,PAPI_FML_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:MULT_FLOPS
PRESET,PAPI_FAD_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ADD_SUB_FLOPS
PRESET,PAPI_FDV_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:DIV_FLOPS
PRESET,PAPI_FSQ_INS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:DIV_FLOPS
#
#
CPU,amd64_fam19h_zen4
CPU,amd64_fam1ah_zen5
PRESET,PAPI_BR_INS,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_CN,NOT_DERIVED,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_UCN,NOT_DERIVED,RETIRED_UNCONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_TKN,DERIVED_SUB,RETIRED_TAKEN_BRANCH_INSTRUCTIONS,RETIRED_UNCONDITIONAL_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_NTK,DERIVED_SUB,RETIRED_BRANCH_INSTRUCTIONS,RETIRED_TAKEN_BRANCH_INSTRUCTIONS
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
PRESET,PAPI_BR_PRC,DERIVED_SUB,RETIRED_CONDITIONAL_BRANCH_INSTRUCTIONS,RETIRED_BRANCH_INSTRUCTIONS_MISPREDICTED
PRESET,PAPI_FP_OPS,NOT_DERIVED,RETIRED_SSE_AVX_FLOPS:ANY
PRESET,PAPI_FP_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_ALL,RETIRED_FP_OPS_BY_TYPE:SCALAR_ALL
PRESET,PAPI_VEC_INS,NOT_DERIVED,RETIRED_FP_OPS_BY_TYPE:VECTOR_ALL
PRESET,PAPI_FMA_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_MAC,RETIRED_FP_OPS_BY_TYPE:SCALAR_MAC
PRESET,PAPI_FML_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_MUL,RETIRED_FP_OPS_BY_TYPE:SCALAR_MUL
PRESET,PAPI_FAD_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_ADD,RETIRED_FP_OPS_BY_TYPE:SCALAR_ADD
PRESET,PAPI_FDV_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_DIV,RETIRED_FP_OPS_BY_TYPE:SCALAR_DIV
PRESET,PAPI_FSQ_INS,DERIVED_ADD,RETIRED_FP_OPS_BY_TYPE:VECTOR_SQRT,RETIRED_FP_OPS_BY_TYPE:SCALAR_SQRT
PRESET,PAPI_TOT_INS,NOT_DERIVED,RETIRED_INSTRUCTIONS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES_NOT_IN_HALT
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1_DTLB_MISS:TLB_RELOAD_1G_L2_MISS:TLB_RELOAD_2M_L2_MISS:TLB_RELOAD_COALESCED_PAGE_MISS:TLB_RELOAD_4K_L2_MISS:TLB_RELOAD_1G_L2_HIT:TLB_RELOAD_2M_L2_HIT:TLB_RELOAD_COALESCED_PAGE_HIT:TLB_RELOAD_4K_L2_HIT
PRESET,PAPI_L1_DCA,NOT_DERIVED,LS_DISPATCH:LD_ST_DISPATCH:STORE_DISPATCH:LD_DISPATCH
PRESET,PAPI_L2_DCM,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C
PRESET,PAPI_L2_DCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X
PRESET,PAPI_TLB_IM,DERIVED_ADD,L1_ITLB_MISS_L2_ITLB_HIT,L1_ITLB_MISS_L2_ITLB_MISS:COALESCED4K:IF1G:IF2M:IF4K
PRESET,PAPI_L2_ICR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ
PRESET,PAPI_L2_ICA,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:CACHEABLE_IC_READ:L2_HW_PF
PRESET,PAPI_L2_ICM,DERIVED_SUB,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_HIT_X:IC_FILL_HIT_S
PRESET,PAPI_L2_TCH,NOT_DERIVED,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C_S:LS_RD_BLK_L_HIT_X:LS_RD_BLK_L_HIT_S:LS_RD_BLK_X:IC_FILL_HIT_X:IC_FILL_HIT_S
PRESET,PAPI_L2_TCM,DERIVED_ADD,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:LS_RD_BLK_C,CORE_TO_L2_CACHEABLE_REQUEST_ACCESS_STATUS:IC_FILL_MISS
#
CPU,amd64_fam19h_zen4
PRESET,PAPI_L1_DCM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X
PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S:CHANGE_TO_X
#
CPU,amd64_fam1ah_zen5
CPU,amd64_fam1ah_zen5_l3
PRESET,PAPI_L1_DCM,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S
PRESET,PAPI_L2_DCR,NOT_DERIVED,REQUESTS_TO_L2_GROUP1:RD_BLK_L:RD_BLK_X:LS_RD_BLK_C_S
# TODO: Investigate additional L3-related Zen5 presets.


CPU,Intel architectural PMU
CPU,ix86arch
#
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,RETIRED_MISPREDICTED_BRANCH_INSTRUCTIONS
#
# Intel Atom
CPU,Intel Atom
CPU,atom
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_DCM,DERIVED_SUB,L2_RQSTS:SELF:MESI,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES
#PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE:LD:ST
PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE:LD,L1D_CACHE:ST
PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_CA_SNP,NOT_DERIVED,EXT_SNOOP:SELF:MESI
PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED,DATA_TLB_MISSES:DTLB_MISS
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:ALL_DECODED
PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV
#PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
#PRESET,PAPI_FP_INS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR
PRESET,PAPI_FP_INS,NOT_DERIVED,SIMD_INST_RETIRED:ANY
#PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_COMP_OPS_EXE:ANY_AR
#PRESET,PAPI_FP_OPS,NOT_DERIVED,SIMD_UOPS_EXEC:AR
PRESET,PAPI_FP_OPS,DERIVED_ADD,SIMD_INST_RETIRED:ANY,X87_COMP_OPS_EXE:ANY_AR
PRESET,PAPI_FML_INS,NOT_DERIVED,MUL:AR
PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV:AR
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
# Intel Atom Silvermont
CPU,slm
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,DERIVED_SUB,ICACHE:ACCESSES,ICACHE:MISSES
PRESET,PAPI_L1_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES
#
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
#
PRESET,PAPI_RES_STL,NOT_DERIVED,UOPS_RETIRED:STALLS
#
#PRESET,PAPI_FP_INS,NOT_DERIVED,UOPS_RETIRED:X87
PRESET,PAPI_FML_INS,NOT_DERIVED,UOPS_RETIRED:MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED,UOPS_RETIRED:DIV
#
CPU,Intel Nehalem
CPU,Intel Westmere
CPU,nhm
CPU,nhm_ex
CPU,wsm
CPU,wsm_dp
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I:READS
PRESET,PAPI_L1_ICH,NOT_DERIVED,L1I:HITS
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPL
#PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:SELF:MESI
#PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
#PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
# OLD VALUE PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_RQSTS:MISS,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L2_DCM,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
# OLD VALUE PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_RQSTS:MISS
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:LD_MISS
#PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
# OLD VALUE PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_DATA_RQSTS:ANY
PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPL
# OLD VALUE PRESET,PAPI_L2_DCR,DERIVED_SUB,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:LOADS
#PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:IFETCH_HIT
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:REFERENCES, L2_RQSTS:MISS
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES
# OLD VALUE PRESET,PAPI_L2_TCR,NOT_DERIVED,L2_RQSTS:LOADS
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:LOADS,L2_RQSTS:IFETCHES
#PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_L1_ICR,NOT_DERIVED,L1I:READS
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:LOADS
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_WRITE:RFO_MESI
PRESET,PAPI_L1_TCM,DERIVED_SUB,L2_RQSTS:REFERENCES,L2_RQSTS:PREFETCHES
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:LD_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_WRITE:RFO_MESI
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:IFETCHES
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFOS
PRESET,PAPI_L3_DCA,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,L2_RQSTS:LD_MISS
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L3_TCR,DERIVED_ADD,L2_RQSTS:LD_MISS,L2_RQSTS:IFETCH_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:LOADS,MEM_INST_RETIRED:STORES
#
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:STORES
#
#PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
#PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
#PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:ANY
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY
PRESET,PAPI_TLB_TL,DERIVED_ADD,ITLB_MISSES:ANY, DTLB_MISSES:ANY
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_EXEC:TAKEN
PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_EXEC:ANY, BR_INST_EXEC:TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC:ANY
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_EXEC:ANY
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_EXEC:COND
PRESET,PAPI_BR_UCN,NOT_DERIVED,BR_INST_EXEC:DIRECT
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_EXEC:COND, BR_MISP_EXEC:COND
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP
# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP
# PAPI_FP_OPS counts single and double precision SCALAR operations
# PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION:SSE_DOUBLE_PRECISION
# According to Stephane (Jan 2010), it's not allowed to combine unit masks for FP_COMP_OPS_EXE;
# we have to use two counters instead
#PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION
PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_FP,FP_COMP_OPS_EXE:X87
# PAPI_SP_OPS = single precision scalar ops + 3 * packed ops
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE:SSE_SINGLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_DOUBLE_PRECISION,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_VEC_SP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED
PRESET,PAPI_VEC_DP,NOT_DERIVED,FP_COMP_OPS_EXE:SSE_FP_PACKED
#PRESET,PAPI_FML_INS,NOT_DERIVED,MUL
#PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV
#PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
# Not available on Westmere
#
CPU,Intel Nehalem
CPU,nhm
CPU,nhm_ex
#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT:RCV
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF:ANY
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF:ANY,L1D:REPL
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF:ANY,L1I:READS
#
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_LD:MESI
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_ST:MESI
PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_CACHE_LD:MESI,L1I:READS
PRESET,PAPI_L2_TCW,NOT_DERIVED,L1D_CACHE_ST:MESI
#
# Intel SandyBridge and IvyBridge
CPU,snb
CPU,snb_ep
CPU,ivb
CPU,ivb_ep
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTION_RETIRED
#
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE:MISSES,L1D:REPLACEMENT
#
PRESET,PAPI_L2_DCM,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_STORE_LOCK_RQSTS:ALL
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
#
PRESET,PAPI_L3_DCA,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L3_TCR,DERIVED_SUB,LAST_LEVEL_CACHE_REFERENCES,L2_RQSTS:RFO_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:RFO_MISS
#
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:ALL_BRANCHES
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:CAUSES_A_WALK
#
PRESET,PAPI_FDV_INS,NOT_DERIVED,ARITH:FPU_DIV
PRESET,PAPI_STL_ICY,NOT_DERIVED,ILD_STALL:IQ_FULL
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOP_RETIRED:ANY_STORES
#
# Counts scalars only; no SSE or AVX is counted; includes speculative
PRESET,PAPI_FP_INS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87
PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:X87
#
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|N2|8|*|+|+|,FP_COMP_OPS_EXE:SSE_FP_SCALAR_SINGLE,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|N2|4|*|+|+|,FP_COMP_OPS_EXE:SSE_SCALAR_DOUBLE,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|4|*|N1|8|*|+|,FP_COMP_OPS_EXE:SSE_PACKED_SINGLE,SIMD_FP_256:PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|2|*|N1|4|*|+|,FP_COMP_OPS_EXE:SSE_FP_PACKED_DOUBLE,SIMD_FP_256:PACKED_DOUBLE
#
# Intel SandyBridge only
CPU,snb
CPU,snb_ep
#
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:RFO_ANY
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_RD_HIT,L2_RQSTS:RFO_HITS
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK
#
# Intel IvyBridge only
CPU,ivb
CPU,ivb_ep
#
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_RQSTS:ALL_RFO
PRESET,PAPI_L2_DCH,DERIVED_ADD,L2_RQSTS:DEMAND_DATA_RD_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:ALL_BRANCHES
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:COND,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:DEMAND_LD_MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:CAUSES_A_WALK
#PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INTERRUPTS
#

# Intel Haswell events
# Using also for Broadwell events, this is what the Linux kernel does
CPU,hsw
CPU,hsw_ep
CPU,bdw
CPU,bdw_ep
CPU,skl
# Note, libpfm4 treats Kaby Lake as just a form of skylake
CPU,kbl
CPU,skx
# Note, libpfm4 treats Cascade Lake-X as just a form of skylake-X
CPU,clx
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:THREAD_P
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
#PRESET,PAPI_REF_CYC,NOT_DERIVED,CPU_CLK_THREAD_UNHALTED:REF_XCLK
# Loads and stores
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ALL_STORES
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ALL_LOADS,MEM_UOPS_RETIRED:ALL_STORES
# L1 cache
#PRESET,PAPI_L1_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_HIT
#PRESET,PAPI_L1_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L1_MISS
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
# Added by FMB
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
# L2 cache
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES
# NOTE on IVB it is PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
#PRESET,PAPI_L2_DCH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT
#PRESET,PAPI_L2_DCM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:REFERENCES
#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT
#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS
# Added by FMB
PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
# L3 cache
#PRESET,PAPI_L3_TCA,NOT_DERIVED,LONGEST_LAT_CACHE:REFERENCE
#PRESET,PAPI_L3_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT
#PRESET,PAPI_L3_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS
# Added by FMB
PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_DCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L3_TCR,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:DEMAND_RFO_MISS
PRESET,PAPI_L3_TCW,NOT_DERIVED,L2_RQSTS:DEMAND_RFO_MISS
# SMP
PRESET,PAPI_CA_SNP,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_ANY
PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:ALL_DATA_RD
PRESET,PAPI_CA_CLN,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_RFO
# TLB
PRESET,PAPI_TLB_DM,DERIVED_ADD,DTLB_LOAD_MISSES:MISS_CAUSES_A_WALK,DTLB_STORE_MISSES:MISS_CAUSES_A_WALK
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES:MISS_CAUSES_A_WALK
# Stalls
PRESET,PAPI_MEM_WCY,NOT_DERIVED,RESOURCE_STALLS:SB
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
PRESET,PAPI_STL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=1:i=1
PRESET,PAPI_FUL_ICY,DERIVED_ADD,IDQ:ALL_DSB_CYCLES_4_UOPS,IDQ:ALL_MITE_CYCLES_4_UOPS
PRESET,PAPI_FUL_CCY,NOT_DERIVED,UOPS_RETIRED:ALL:c=4
# Branches
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:CONDITIONAL
PRESET,PAPI_BR_TKN,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:NOT_TAKEN
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:CONDITIONAL
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:CONDITIONAL,BR_MISP_RETIRED:CONDITIONAL
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES

CPU,hsw
CPU,hsw_ep
CPU,bdw
CPU,bdw_ep
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_TRANS:DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_TRANS:L1D_WB
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_TRANS:RFO
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_TRANS:RFO
PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:L2_PF_MISS
PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ:EMPTY
PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_FWD

CPU,hsw
CPU,hsw_ep
PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HITM

CPU,bdw
CPU,bdw_ep
PRESET,PAPI_CA_INV,NOT_DERIVED,OFFCORE_RESPONSE_0:HITM

# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE
# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE

CPU,skl
CPU,skx
CPU,clx
# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE

PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_RQSTS:ALL_RFO
PRESET,PAPI_L2_DCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_L2_TCW,DERIVED_ADD,L2_RQSTS:DEMAND_RFO_HIT,L2_RQSTS:RFO_HIT
PRESET,PAPI_PRF_DM,NOT_DERIVED,L2_RQSTS:PF_MISS
PRESET,PAPI_STL_ICY,NOT_DERIVED,IDQ_UOPS_NOT_DELIVERED:CYCLES_0_UOPS_DELIV_CORE

PRESET,PAPI_CA_ITV,NOT_DERIVED,OFFCORE_RESPONSE_0:SNP_HIT_WITH_FWD


# End of hsw,bdw,skl,clx list
#

# Intel Ice Lake SP events
CPU,icx
CPU,icl
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
# Loads and stores
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_STORES
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:ALL_LOADS,MEM_INST_RETIRED:ALL_STORES
# L1 cache
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
# L2 cache
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_REFERENCES
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_TCH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_HIT
#PRESET,PAPI_L2_TCM,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L2_MISS
PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
#PRESET,PAPI_L2_LDH,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_HIT
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
PRESET,PAPI_L2_TCA,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_REFERENCES,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
# L3 cache
PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
#PRESET,PAPI_L3_LDH,NOT_DERIVED,MEM_LOAD_UOPS_RETIRED:L3_HIT
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS
PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES
# SMP
PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:ALL_DATA_RD
# Branches
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:COND_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:COND_NTAKEN
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:COND
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:COND
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES
#FLOPs
# PAPI_DP_OPS = FP_ARITH:SCALAR_DOUBLE + 2*FP_ARITH:128B_PACKED_DOUBLE + 4*256B_PACKED_DOUBLE + 8*512B_PACKED_DOUBLE
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
# PAPI_SP_OPS = FP_ARITH:SCALAR_SINGLE + 4*FP_ARITH:128B_PACKED_SINGLE + 8*256B_PACKED_SINGLE + 16*512B_PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|N4|+|N5|2|*|+|N6|4|*|+|N7|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
PRESET,PAPI_FP_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|N6|N7|+|+|+|+|+|+|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_DOUBLE,FP_ARITH:128B_PACKED_DOUBLE,FP_ARITH:256B_PACKED_DOUBLE,FP_ARITH:512B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH:SCALAR_SINGLE,FP_ARITH:128B_PACKED_SINGLE,FP_ARITH:256B_PACKED_SINGLE,FP_ARITH:512B_PACKED_SINGLE
PRESET,PAPI_VEC_INS,DERIVED_POSTFIX,N0|N1|N2|N3|N4|N5|+|+|+|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
# End of icx, icl list

# Intel Sapphire Rapids and Emerald Rapids events
CPU,emr
CPU,spr
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:THREAD_P
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED:ANY_P
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
# FLOPs
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE
PRESET,PAPI_HP_OPS,DERIVED_POSTFIX,N0|N1|8|*|+|N2|16|*|+|N3|32|*|+|,FP_ARITH_INST_RETIRED2:SCALAR_HALF,FP_ARITH_INST_RETIRED2:128B_PACKED_HALF,FP_ARITH_INST_RETIRED2:256B_PACKED_HALF,FP_ARITH_INST_RETIRED2:512B_PACKED_HALF
#PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|4|*|+|N2|8|*|+|N3|16|*|+|N4|+|N5|2|*|+|N6|4|*|+|N7|8|*|+|,FP_ARITH_INST_RETIRED:SCALAR_SINGLE,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:SCALAR_DOUBLE,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
PRESET,PAPI_FP_INS,DERIVED_POSTFIX,N0|N1|N2|N3|+|+|+|,FP_ARITH_INST_RETIRED:SCALAR,FP_ARITH_INST_RETIRED:VECTOR,FP_ARITH_INST_RETIRED2:SCALAR,FP_ARITH_INST_RETIRED2:VECTOR
PRESET,PAPI_VEC_DP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:256B_PACKED_DOUBLE,FP_ARITH_INST_RETIRED:512B_PACKED_DOUBLE
PRESET,PAPI_VEC_SP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH_INST_RETIRED:128B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:256B_PACKED_SINGLE,FP_ARITH_INST_RETIRED:512B_PACKED_SINGLE
PRESET,PAPI_VEC_HP,DERIVED_POSTFIX,N0|N1|N2|+|+|,FP_ARITH_INST_RETIRED2:128B_PACKED_HALF,FP_ARITH_INST_RETIRED2:256B_PACKED_HALF,FP_ARITH_INST_RETIRED2:512B_PACKED_HALF
PRESET,PAPI_VEC_INS,DERIVED_ADD,FP_ARITH_INST_RETIRED:VECTOR,FP_ARITH_INST_RETIRED2:VECTOR
# Branches
PRESET,PAPI_BR_UCN,DERIVED_SUB,BR_INST_RETIRED:ALL_BRANCHES,BR_INST_RETIRED:COND
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:COND
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:COND_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:COND_NTAKEN
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISP_RETIRED:COND
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED:COND,BR_MISP_RETIRED:COND
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED:ALL_BRANCHES
# Instruction Caches
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_ICH,NOT_DERIVED,L2_RQSTS:CODE_RD_HIT
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L3_ICA,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_ICR,NOT_DERIVED,L2_RQSTS:CODE_RD_MISS
# Loads and stores
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_INST_RETIRED:ALL_STORES
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_INST_RETIRED:ALL_LOADS,MEM_INST_RETIRED:ALL_STORES
# Data Caches
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L2_DCA,NOT_DERIVED,L1D:REPLACEMENT
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_RQSTS:ALL_DEMAND_DATA_RD
#PRESET,PAPI_L2_DCM,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L2_DCM,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_RQSTS:DEMAND_DATA_RD_MISS
#PRESET,PAPI_L3_DCA,DERIVED_SUB,LLC_REFERENCES,L2_RQSTS:CODE_RD_MISS
PRESET,PAPI_L3_DCA,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD
PRESET,PAPI_L3_DCR,NOT_DERIVED,OFFCORE_REQUESTS:DEMAND_DATA_RD
PRESET,PAPI_L3_LDM,NOT_DERIVED,MEM_LOAD_RETIRED:L3_MISS
# SMP
PRESET,PAPI_CA_SHR,NOT_DERIVED,OFFCORE_REQUESTS:DATA_RD
# Total Caches
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCA,DERIVED_ADD,L1D:REPLACEMENT,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_RQSTS:ALL_DEMAND_DATA_RD,L2_RQSTS:ALL_CODE_RD
PRESET,PAPI_L3_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L3_TCM,NOT_DERIVED,LLC_MISSES
# End of spr list

#
# Intel MIC / Xeon-Phi / Knights Landing
# Intel Knights Mill
#
CPU,knl
CPU,knm
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE:MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE:ACCESSES
PRESET,PAPI_L1_ICH,NOT_DERIVED,ICACHE:HIT
#
PRESET,PAPI_L1_DCA,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST
PRESET,PAPI_L1_DCM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS
PRESET,PAPI_L1_TCM,DERIVED_ADD,MEM_UOPS_RETIRED:LD_DCU_MISS,ICACHE:MISSES
PRESET,PAPI_L1_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_DCU_MISS
#
PRESET,PAPI_L2_TCA,NOT_DERIVED,LLC_REFERENCES
PRESET,PAPI_L2_TCM,NOT_DERIVED,LLC_MISSES
PRESET,PAPI_L2_TCH,DERIVED_SUB,LLC_REFERENCES,LLC_MISSES
PRESET,PAPI_L2_LDM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_L2_MISS
PRESET,PAPI_LD_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_LD
PRESET,PAPI_SR_INS,NOT_DERIVED,MEM_UOPS_RETIRED:ANY_ST
PRESET,PAPI_LST_INS,DERIVED_ADD,MEM_UOPS_RETIRED:ANY_LD,MEM_UOPS_RETIRED:ANY_ST
#
PRESET,PAPI_TLB_DM,NOT_DERIVED,MEM_UOPS_RETIRED:LD_UTLB_MISS
#
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_UCN,DERIVED_SUB,BRANCH_INSTRUCTIONS_RETIRED,BR_INST_RETIRED:JCC
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN_JCC
PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED:JCC,BR_INST_RETIRED:TAKEN_JCC
#
PRESET,PAPI_RES_STL,NOT_DERIVED,RS_FULL_STALL:ANY
PRESET,PAPI_STL_ICY,NOT_DERIVED,NO_ALLOC_CYCLES:ANY
#
# End of knl,knm list

CPU,Intel Core2
CPU,Intel Core
CPU,core
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_MISSES
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_READS
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_READS,L1I_MISSES
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_REPL
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_ALL_REF
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_ALL_REF,L1D_REPL
PRESET,PAPI_L1_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_ALL_REF,L1I_READS
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:SELF:ANY,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_IN:SELF
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_ST:SELF:MESI
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:SELF:ANY:MESI
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:SELF:MESI
PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:SELF:MESI,BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:SELF:ANY:MESI,L2_LINES_IN:SELF:ANY
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:SELF:ANY:MESI
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:SELF:ANY:MESI,L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:SELF:MESI
#
PRESET,PAPI_LD_INS,NOT_DERIVED,INST_RETIRED:LOADS
PRESET,PAPI_SR_INS,NOT_DERIVED,INST_RETIRED:STORES
#
PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRANS_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB:MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISSES:ANY
#
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_INST_RETIRED:TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,BR_INST_RETIRED:PRED_NOT_TAKEN:MISPRED_NOT_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_EXEC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISSP_EXEC
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_CND_EXEC
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_CND_EXEC,BR_CND_MISSP_EXEC
#
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MACRO_INSTS:DECODED
PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RCV
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS:ANY
#
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_OPS_EXE
# This is an alternate definition of OPS that produces no error with calibrate
# the previous definition was identical to FP_INS
# PRESET,PAPI_FP_OPS,NOT_DERIVED,X87_OPS_RETIRED:ANY
# PRESET,PAPI_FP_OPS,DERIVED_ADD, FP_COMP_OPS_EXE, SIMD_COMP_INST_RETIRED:SCALAR_DOUBLE:PACKED_DOUBLE:SCALAR_SINGLE:PACKED_SINGLE
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_OPS_EXE
# PAPI_SP_OPS = FP_COMP_OPS_EXE + 3 * SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|N1|3|*|+|,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_DP_OPS,DERIVED_ADD,FP_COMP_OPS_EXE,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE
PRESET,PAPI_VEC_SP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_SINGLE
PRESET,PAPI_VEC_DP,NOT_DERIVED,SIMD_COMP_INST_RETIRED:PACKED_DOUBLE
#
PRESET,PAPI_FML_INS,NOT_DERIVED,MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED:VECTOR
#
CPU,Intel Core Duo/Solo
CPU,coreduo
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,UNHALTED_CORE_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,UNHALTED_REFERENCE_CYCLES
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_INSTRUCTIONS_RETIRED
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_TAKEN_RET
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_RETIRED
PRESET,PAPI_L2_TCM,NOT_DERIVED,LAST_LEVEL_CACHE_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,LAST_LEVEL_CACHE_REFERENCES
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_COMP_INSTR_RET
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_COMP_INSTR_RET
#
PRESET,PAPI_L1_DCM,NOT_DERIVED, DCACHE_REPL
PRESET,PAPI_L1_ICM,NOT_DERIVED, L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_DCM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICM,NOT_DERIVED, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L1_TCM,NOT_DERIVED, L2_RQSTS:SELF:MESI
#PRESET,PAPI_L2_TCM,NOT_DERIVED, L2_LINES_IN:SELF:ANY
PRESET,PAPI_CA_SHR,NOT_DERIVED, L2_RQSTS:SELF:ANY:S_STATE
PRESET,PAPI_CA_CLN,NOT_DERIVED, BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED, BUS_TRANS_INVAL:SELF
PRESET,PAPI_TLB_IM,NOT_DERIVED, ITLB_MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED, DTLB_MISS
PRESET,PAPI_L1_LDM,NOT_DERIVED, L2_LD:SELF:MESI
PRESET,PAPI_L1_STM,NOT_DERIVED, L2_ST:SELF:MESI
PRESET,PAPI_L2_LDM,DERIVED_SUB, L2_LINES_IN:SELF:ANY, L2_M_LINES_IN:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED, L2_M_LINES_IN:SELF
PRESET,PAPI_BTAC_M,NOT_DERIVED, PREF_RQSTS_DN
PRESET,PAPI_HW_INT,NOT_DERIVED, HW_INT_RX
PRESET,PAPI_BR_CN,NOT_DERIVED, BR_CND_EXEC
PRESET,PAPI_BR_TKN,NOT_DERIVED, BR_TAKEN_RET
PRESET,PAPI_BR_NTK,DERIVED_SUB, BR_INSTR_RET,BR_TAKEN_RET
PRESET,PAPI_BR_MSP,NOT_DERIVED, BR_MISSP_EXEC
PRESET,PAPI_BR_PRC,DERIVED_SUB, BR_INSTR_RET,BR_MISPRED_RET
PRESET,PAPI_TOT_IIS,NOT_DERIVED, INSTR_DECODED
PRESET,PAPI_RES_STL,NOT_DERIVED, RESOURCE_STALL
PRESET,PAPI_L1_DCH,DERIVED_SUB, DATA_MEM_REF, DCACHE_REPL
PRESET,PAPI_L1_DCA,NOT_DERIVED, DATA_MEM_REF
PRESET,PAPI_L2_DCA,DERIVED_ADD, L2_LD:SELF:MESI, L2_ST:SELF:MESI
PRESET,PAPI_L2_DCR,NOT_DERIVED, L2_LD:SELF:MESI
PRESET,PAPI_L2_DCW,NOT_DERIVED, L2_ST:SELF:MESI
PRESET,PAPI_L1_ICH,DERIVED_SUB, BUS_TRANS_IFETCH:SELF, L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_ICH,DERIVED_SUB, L2_IFETCH:SELF:MESI, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L1_ICA,NOT_DERIVED, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED, L2_IFETCH:SELF:MESI
PRESET,PAPI_L1_ICR,NOT_DERIVED, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_ICR,NOT_DERIVED, L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCH,DERIVED_SUB, L2_RQSTS:SELF:ANY:MESI, L2_LINES_IN:SELF:ANY
PRESET,PAPI_L1_TCA,DERIVED_ADD, DATA_MEM_REF, BUS_TRANS_IFETCH:SELF
PRESET,PAPI_L2_TCA,NOT_DERIVED, L2_RQSTS:SELF:ANY:MESI
PRESET,PAPI_L2_TCR,DERIVED_ADD, L2_LD:SELF:MESI, L2_IFETCH:SELF:MESI
PRESET,PAPI_L2_TCW,NOT_DERIVED, L2_ST:SELF:MESI
PRESET,PAPI_FML_INS,NOT_DERIVED, MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED, DIV
#
CPU,Intel PentiumIII
CPU,Intel P6 Processor Family
CPU,p6
#
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN,BUS_TRAN_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN,L2_M_LINES_INM
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:M:E:S:I,L2_LINES_IN
#
CPU,Intel PentiumM
CPU,Intel Pentium M
CPU,pm
#
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH,BUS_TRAN_IFETCH:SELF
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH
PRESET,PAPI_L2_LDM,DERIVED_SUB,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH,L2_M_LINES_INM
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_RQSTS:M:E:S:I,L2_LINES_IN:ONLY_HW_PREFETCH:NON_HW_PREFETCH
#
CPU,Intel P6
CPU,Intel PentiumIII
CPU,Intel PentiumM
CPU,Intel P6 Processor Family
CPU,Intel Pentium Pro
CPU,Intel Pentium II
CPU,Intel Pentium M
CPU,p6
CPU,ppro
CPU,pii
CPU,pm
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED
PRESET,PAPI_L1_DCM,NOT_DERIVED,DCU_LINES_IN
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_IFETCH:M:E:S:I
PRESET,PAPI_L1_TCM,NOT_DERIVED,L2_RQSTS:M:E:S:I
PRESET,PAPI_L1_LDM,NOT_DERIVED,L2_LD:M:E:S:I
PRESET,PAPI_L1_STM,NOT_DERIVED,L2_ST:M:E:S:I
PRESET,PAPI_L1_DCH,DERIVED_SUB,DATA_MEM_REFS,DCU_LINES_IN
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_MEM_REFS
PRESET,PAPI_L1_ICH,DERIVED_SUB,IFU_IFETCH,L2_IFETCH:M:E:S:I
PRESET,PAPI_L1_ICA,NOT_DERIVED,IFU_IFETCH
PRESET,PAPI_L1_ICR,NOT_DERIVED,IFU_IFETCH
PRESET,PAPI_L1_TCA,DERIVED_ADD,DATA_MEM_REFS,IFU_IFETCH
#
PRESET,PAPI_L2_ICM,NOT_DERIVED,BUS_TRAN_IFETCH:SELF
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_M_LINES_INM
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2_LD:M:E:S:I,L2_ST:M:E:S:I
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_LD:M:E:S:I
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_ST:M:E:S:I
PRESET,PAPI_L2_ICH,DERIVED_SUB,L2_IFETCH:M:E:S:I,BUS_TRAN_IFETCH:SELF
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_IFETCH:M:E:S:I
PRESET,PAPI_L2_ICR,NOT_DERIVED,L2_IFETCH:M:E:S:I
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_RQSTS:M:E:S:I
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_LD:M:E:S:I,L2_IFETCH:M:E:S:I
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_ST:M:E:S:I
#
PRESET,PAPI_CA_SHR,NOT_DERIVED,L2_RQSTS:S
PRESET,PAPI_CA_CLN,NOT_DERIVED,BUS_TRANS_RFO:SELF
PRESET,PAPI_CA_ITV,NOT_DERIVED,BUS_TRAN_INVAL:SELF
#
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_HW_INT,NOT_DERIVED,HW_INT_RX
PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DECODED
PRESET,PAPI_RES_STL,NOT_DERIVED,RESOURCE_STALLS
#
PRESET,PAPI_BTAC_M,NOT_DERIVED,BTB_MISSES
PRESET,PAPI_BR_CN,NOT_DERIVED,BR_INST_RETIRED
PRESET,PAPI_BR_TKN,NOT_DERIVED,BR_TAKEN_RETIRED
PRESET,PAPI_BR_NTK,DERIVED_SUB,BR_INST_RETIRED,BR_TAKEN_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISS_PRED_RETIRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_INST_RETIRED,BR_MISS_PRED_RETIRED
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_INST_RETIRED
#
PRESET,PAPI_FP_INS,NOT_DERIVED,FLOPS
PRESET,PAPI_FP_OPS,NOT_DERIVED,FLOPS
PRESET,PAPI_FML_INS,NOT_DERIVED,MUL
PRESET,PAPI_FDV_INS,NOT_DERIVED,DIV
#
# This is an example of multiple processor names matching the same table
CPU,Intel Pentium4
CPU,Intel Pentium4 L3
CPU,Pentium4/Xeon/EM64T
CPU,netburst
CPU,netburst_p
#
# Note: the proper event is GLOBAL_POWER_EVENTS:RUNNING
#       but the kernel grabs that for the watchdog timer
#       and suggests "" is equivalent
#PRESET,PAPI_TOT_CYC,NOT_DERIVED,GLOBAL_POWER_EVENTS:RUNNING
PRESET,PAPI_TOT_CYC,NOT_DERIVED,execution_event:nbogus0:nbogus1:nbogus2:nbogus3:bogus0:bogus1:bogus2:bogus3:cmpl:thr=15
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_RETIRED:NBOGUSNTAG
PRESET,PAPI_RES_STL, NOT_DERIVED, resource_stall:SBFULL
PRESET,PAPI_BR_INS, NOT_DERIVED, branch_retired:MMNP:MMNM:MMTP:MMTM
PRESET,PAPI_BR_TKN, NOT_DERIVED, branch_retired:MMTP:MMTM
PRESET,PAPI_BR_NTK, NOT_DERIVED, branch_retired:MMNP:MMNM
PRESET,PAPI_BR_MSP, NOT_DERIVED, branch_retired:MMNM:MMTM
PRESET,PAPI_BR_PRC, NOT_DERIVED, branch_retired:MMNP:MMTP
PRESET,PAPI_TLB_DM, NOT_DERIVED, page_walk_type:DTMISS
PRESET,PAPI_TLB_IM, NOT_DERIVED, page_walk_type:ITMISS
PRESET,PAPI_TLB_TL, NOT_DERIVED, page_walk_type:DTMISS:ITMISS
PRESET,PAPI_LD_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGLOADS
PRESET,PAPI_SR_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGSTORES
PRESET,PAPI_LST_INS, DERIVED_CMPD, front_end_event:NBOGUS, uops_type:TAGLOADS:TAGSTORES
PRESET,PAPI_FP_INS, DERIVED_CMPD, execution_event:NBOGUS0, x87_FP_uop:ALL:TAG0,NOTE,"PAPI_FP_INS counts only retired x87 uops tagged with 0. If you add other native events tagged with 0, their counts will be included in PAPI_FP_INS"
PRESET,PAPI_TOT_IIS, NOT_DERIVED, instr_retired:NBOGUSNTAG:NBOGUSTAG:BOGUSNTAG:BOGUSTAG, NOTE, "Only on model 2 and above"
PRESET,PAPI_L1_ICM, NOT_DERIVED, BPU_fetch_request:TCMISS
PRESET,PAPI_L1_ICA, NOT_DERIVED, uop_queue_writes:FROM_TC_BUILD:FROM_TC_DELIVER
PRESET,PAPI_L1_LDM, NOT_DERIVED, replay_event:NBOGUS:L1_LD_MISS
PRESET,PAPI_L2_LDM, NOT_DERIVED, replay_event:NBOGUS:L2_LD_MISS
PRESET,PAPI_L2_TCH, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_HITS:RD_2ndL_HITE:RD_2ndL_HITM
PRESET,PAPI_L2_TCM, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_MISS
PRESET,PAPI_L2_TCA, NOT_DERIVED, BSQ_cache_reference:RD_2ndL_MISS:RD_2ndL_HITS:RD_2ndL_HITE:RD_2ndL_HITM
#
CPU,Intel Pentium4 L3
PRESET,PAPI_L3_TCH, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_HITS:RD_3rdL_HITE:RD_3rdL_HITM
PRESET,PAPI_L3_TCM, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_MISS
PRESET,PAPI_L3_TCA, NOT_DERIVED, BSQ_cache_reference:RD_3rdL_MISS:RD_3rdL_HITS:RD_3rdL_HITE:RD_3rdL_HITM
#
CPU,Intel Pentium4 FPU X87
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, x87_FP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired x87 uops tagged with 1."
#
CPU,Intel Pentium4 FPU SSE_SP
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired scalar_SP SSE uops tagged with 1."
#
CPU,Intel Pentium4 FPU SSE_DP
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_DP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired scalar_DP SSE uops tagged with 1."
#
CPU,Intel Pentium4 FPU X87 SSE_SP
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1, x87_FP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired x87 and scalar_SP SSE uops tagged with 1."
#
CPU,Intel Pentium4 FPU X87 SSE_DP
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_DP_uop:ALL:TAG1, x87_FP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired x87 and scalar_DP SSE uops tagged with 1."
#
CPU,Intel Pentium4 FPU SSE_SP SSE_DP
PRESET,PAPI_FP_OPS, DERIVED_CMPD, execution_event:NBOGUS1, scalar_SP_uop:ALL:TAG1, scalar_DP_uop:ALL:TAG1,NOTE,"PAPI_FP_OPS counts retired scalar_SP and scalar_DP SSE uops tagged with 1."
#
CPU,Intel Pentium4 VEC MMX
PRESET,PAPI_VEC_INS, DERIVED_CMPD, execution_event:NBOGUS2, 64bit_MMX_uop:ALL:TAG2, 128bit_MMX_uop:ALL:TAG2,NOTE,"PAPI_VEC_INS counts retired 64bit and 128bit MMX uops tagged with 2."
#
CPU,Intel Pentium4 VEC SSE
PRESET,PAPI_VEC_INS, DERIVED_CMPD, execution_event:NBOGUS2, packed_SP_uop:ALL:TAG2, packed_DP_uop:ALL:TAG2,NOTE,"PAPI_VEC_INS counts retired packed single and double precision SSE uops tagged with 2."
#
CPU,IA-64
#
CPU,dual-core Itanium 2
#
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED
PRESET,PAPI_STL_ICY,NOT_DERIVED,DISP_STALLED
PRESET,PAPI_STL_CCY,NOT_DERIVED,BACK_END_BUBBLE_ALL
PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DISPERSED
PRESET,PAPI_RES_STL,NOT_DERIVED,BE_EXE_BUBBLE_ALL
PRESET,PAPI_FP_STAL,NOT_DERIVED,BE_EXE_BUBBLE_FRALL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2I_READS_ALL_DMND
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_READ_MISSES_ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2I_READS_MISS_ALL
PRESET,PAPI_L2_ICM,NOT_DERIVED,L2I_READS_MISS_ALL
PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISSES
PRESET,PAPI_L3_ICM,NOT_DERIVED,L3_READS_INST_FETCH_MISS:M:E:S:I
PRESET,PAPI_L3_LDM,NOT_DERIVED,L3_READS_ALL_MISS:M:E:S:I
PRESET,PAPI_L3_STM,NOT_DERIVED,L3_WRITES_DATA_WRITE_MISS:M:E:S:I
PRESET,PAPI_L1_LDM,NOT_DERIVED,L1D_READ_MISSES_ALL
PRESET,PAPI_L2_LDM,NOT_DERIVED,L3_READS_ALL_ALL:M:E:S:I
PRESET,PAPI_L2_STM,NOT_DERIVED,L3_WRITES_ALL_ALL:M:E:S:I
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_READS_SET1
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_REFERENCES_ALL
PRESET,PAPI_L3_DCA,NOT_DERIVED,L3_REFERENCES
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READS_SET1
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_REFERENCES_READS
PRESET,PAPI_L3_DCR,NOT_DERIVED,L3_READS_DATA_READ_ALL:M:E:S:I
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_REFERENCES_WRITES
PRESET,PAPI_L3_DCW,NOT_DERIVED,L3_WRITES_DATA_WRITE_ALL:M:E:S:I
PRESET,PAPI_L3_ICH,NOT_DERIVED,L3_READS_DINST_FETCH_HIT:M:E:S:I
PRESET,PAPI_L3_ICR,NOT_DERIVED,L3_READS_INST_FETCH_ALL:M:E:S:I
PRESET,PAPI_L3_TCA,NOT_DERIVED,L3_REFERENCES
PRESET,PAPI_L3_TCR,NOT_DERIVED,L3_READS_ALL_ALL:M:E:S:I
PRESET,PAPI_L3_TCW,NOT_DERIVED,L3_WRITES_ALL_ALL:M:E:S:I
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2DTLB_MISSES
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES_FETCH_L2ITLB
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_EVENT
PRESET,PAPI_BR_PRC,NOT_DERIVED,BR_MISPRED_DETAIL_ALL_CORRECT_PRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_OP_CYCLES_ALL
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED
PRESET,PAPI_TOT_INS,NOT_DERIVED,IA64_INST_RETIRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LOADS_RETIRED
PRESET,PAPI_SR_INS,NOT_DERIVED,STORES_RETIRED
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2I_DEMAND_READS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L3_READS_INST_FETCH_ALL:M:E:S:I
PRESET,PAPI_L1_TCR,NOT_DERIVED,L2I_READS_ALL_ALL
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_REFERENCES_WRITES
#
CPU,itanium2
#
PRESET,PAPI_CA_SNP,NOT_DERIVED,BUS_SNOOPS_SELF
PRESET,PAPI_CA_INV,DERIVED_ADD,BUS_MEM_READ_BRIL_SELF,BUS_MEM_READ_BIL_SELF
PRESET,PAPI_TLB_TL,DERIVED_ADD,ITLB_MISSES_FETCH_L2ITLB,L2DTLB_MISSES
PRESET,PAPI_STL_ICY,NOT_DERIVED,DISP_STALLED
PRESET,PAPI_STL_CCY,NOT_DERIVED,BACK_END_BUBBLE_ALL
PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_DISPERSED
PRESET,PAPI_RES_STL,NOT_DERIVED,BE_EXE_BUBBLE_ALL
PRESET,PAPI_FP_STAL,NOT_DERIVED,BE_EXE_BUBBLE_FRALL
PRESET,PAPI_L2_TCR,DERIVED_ADD,L2_DATA_REFERENCES_L2_DATA_READS,L2_INST_DEMAND_READS,L2_INST_PREFETCHES
PRESET,PAPI_L1_TCM,DERIVED_ADD,L2_INST_DEMAND_READS,L1D_READ_MISSES_ALL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L2_INST_DEMAND_READS
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_READ_MISSES_ALL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_MISSES
PRESET,PAPI_L2_DCM, DERIVED_SUB,L2_MISSES,L3_READS_INST_FETCH_ALL
PRESET,PAPI_L2_ICM,NOT_DERIVED,L3_READS_INST_FETCH_ALL
PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISSES
PRESET,PAPI_L3_ICM,NOT_DERIVED,L3_READS_INST_FETCH_MISS
PRESET,PAPI_L3_DCM, DERIVED_ADD,L3_READS_DATA_READ_MISS,L3_WRITES_DATA_WRITE_MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,L3_READS_ALL_MISS
PRESET,PAPI_L3_STM,NOT_DERIVED,L3_WRITES_DATA_WRITE_MISS
PRESET,PAPI_L1_LDM,DERIVED_ADD,L1D_READ_MISSES_ALL,L2_INST_DEMAND_READS
PRESET,PAPI_L2_LDM,NOT_DERIVED,L3_READS_ALL_ALL
PRESET,PAPI_L2_STM,NOT_DERIVED,L3_WRITES_ALL_ALL
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_READS_SET1,L1D_READ_MISSES_ALL
PRESET,PAPI_L2_DCH,DERIVED_SUB,L2_DATA_REFERENCES_L2_ALL,L2_MISSES
PRESET,PAPI_L3_DCH,DERIVED_ADD,L3_READS_DATA_READ_HIT,L3_WRITES_DATA_WRITE_HIT
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_READS_SET1
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2_DATA_REFERENCES_L2_ALL
PRESET,PAPI_L3_DCA,DERIVED_ADD,L3_READS_DATA_READ_ALL,L3_WRITES_DATA_WRITE_ALL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READS_SET1
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_READS
PRESET,PAPI_L3_DCR,NOT_DERIVED,L3_READS_DATA_READ_ALL
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_WRITES
PRESET,PAPI_L3_DCW,NOT_DERIVED,L3_WRITES_DATA_WRITE_ALL
PRESET,PAPI_L3_ICH,NOT_DERIVED,L3_READS_DINST_FETCH_HIT
PRESET,PAPI_L1_ICR,DERIVED_ADD,L1I_PREFETCHES,L1I_READS
PRESET,PAPI_L2_ICR,DERIVED_ADD,L2_INST_DEMAND_READS,L2_INST_PREFETCHES
PRESET,PAPI_L3_ICR,NOT_DERIVED,L3_READS_INST_FETCH_ALL
PRESET,PAPI_L1_ICA,DERIVED_ADD,L1I_PREFETCHES,L1I_READS
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2_REFERENCES,L2_MISSES
PRESET,PAPI_L3_TCH,DERIVED_SUB,L3_REFERENCES,L3_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_REFERENCES
PRESET,PAPI_L3_TCA,NOT_DERIVED,L3_REFERENCES
PRESET,PAPI_L3_TCR,NOT_DERIVED,L3_READS_ALL_ALL
PRESET,PAPI_L3_TCW,NOT_DERIVED,L3_WRITES_ALL_ALL
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2DTLB_MISSES
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISSES_FETCH_L2ITLB
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_EVENT
PRESET,PAPI_BR_PRC,NOT_DERIVED,BR_MISPRED_DETAIL_ALL_CORRECT_PRED
PRESET,PAPI_BR_MSP,DERIVED_ADD,BR_MISPRED_DETAIL_ALL_WRONG_PATH,BR_MISPRED_DETAIL_ALL_WRONG_TARGET
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_OPS,NOT_DERIVED,FP_OPS_RETIRED
PRESET,PAPI_TOT_INS,DERIVED_ADD,IA64_INST_RETIRED,IA32_INST_RETIRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LOADS_RETIRED
PRESET,PAPI_SR_INS,NOT_DERIVED,STORES_RETIRED
PRESET,PAPI_L2_ICA,NOT_DERIVED,L2_INST_DEMAND_READS
PRESET,PAPI_L3_ICA,NOT_DERIVED,L3_READS_INST_FETCH_ALL
PRESET,PAPI_L1_TCR,DERIVED_ADD,L1D_READS_SET0,L1I_READS 
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_READS_SET0,L1I_READS 
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2_DATA_REFERENCES_L2_DATA_WRITES
#
CPU,itanium
#
CPU,PPC970
#
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L2_DCR,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR,PM_DATA_FROM_MEM
PRESET,PAPI_L2_DCH,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L1_ICM,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM
PRESET,PAPI_L2_ICA,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM
PRESET,PAPI_L2_ICH,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_MEM
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|-|,PM_FPU0_FIN,PM_FPU1_FIN,PM_FPU_FMA,PM_FPU_STF
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC
PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV
PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT
PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED
PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA
PRESET,PAPI_L1_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_REF_L1,PM_ST_MISS_L1
PRESET,PAPI_L3_DCM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L3_LDM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_MEM
#
CPU,PPC970MP
#
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L2_DCR,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR,PM_DATA_FROM_MEM
PRESET,PAPI_L2_DCH,DERIVED_ADD,PM_DATA_FROM_L2,PM_DATA_FROM_L25_MOD,PM_DATA_FROM_L25_SHR PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_MEM
#PRESET,PAPI_L1_ICM,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM
#PRESET,PAPI_L2_ICA,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD,PM_INST_FROM_MEM
#PRESET,PAPI_L2_ICH,DERIVED_ADD,PM_INST_FROM_L2,PM_INST_FROM_L25_SHR,PM_INST_FROM_L25_MOD PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_MEM
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|-|,PM_FPU0_FIN,PM_FPU1_FIN,PM_FPU_FMA,PM_FPU_STF 
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC
PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV
PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT
PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED
PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA
PRESET,PAPI_L1_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_REF_L1,PM_ST_MISS_L1
PRESET,PAPI_L3_DCM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L3_LDM,NOT_DERIVED,PM_DATA_FROM_MEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_MEM
#
CPU,POWER5
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN
PRESET,PAPI_FP_OPS,DERIVED_ADD,PM_FPU_1FLOP,PM_FPU_FMA,PM_FPU_FMA
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV
PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT
PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED
PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_CR_TA
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER5+
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|N3|+|4|*|+|,PM_FPU_1FLOP,PM_FPU_FMA,PM_FPU_FSQRT,PM_FPU_FDIV
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_FDV_INS,NOT_DERIVED,PM_FPU_FDIV
PRESET,PAPI_FSQ_INS,NOT_DERIVED,PM_FPU_FSQRT
PRESET,PAPI_TLB_DM,NOT_DERIVED,PM_DTLB_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,PM_ITLB_MISS
PRESET,PAPI_TLB_TL,DERIVED_ADD,PM_DTLB_MISS,PM_ITLB_MISS
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_ISSUED
PRESET,PAPI_BR_MSP,DERIVED_ADD,PM_BR_MPRED_CR,PM_BR_MPRED_TA
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_CR_TA
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER6
CPU,power6
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_REF_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FPU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN
# This definition comes from the (unreleased) IBM PM documentation
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|3|*|N1|N2|+|+|,PM_FPU_FSQRT_FDIV,PM_FPU_FLOP,PM_FPU_FMA
# The following counts SQRT and DIV as one FP event instead of 4
#PRESET,PAPI_FP_OPS,DERIVED_ADD,PM_FPU_FLOP,PM_FPU_FMA
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FPU_FIN
# It appears PM_CYC is not widely available
#PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_CYC
# PM_RUN_CYC is in every group; but it doesn't overflow :(
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,NOT_DERIVED,PM_0INST_FETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_REF_L1
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_ST_REF_L1,PM_LD_REF_L1
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN
PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER7
CPU,power7
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1
PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_VSU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN
#
# We'd like to do a 1FLOP + 2*2FLOP + 4*4FLOP + 8*8FLOP + 16*16FLOP, but
# we run out of counters (we have 4, but need 5).  So for now, just assume
# that the vast majority of users won't be using the single precision
# vector FDIV and FSQRT instructions that would tick PM_VSU0_16FLOP.
#
#PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|N4|16|*|+|,PM_VSU_1FLOP,PM_VSU_2FLOP,PM_VSU_4FLOP,PM_VSU_8FLOP,PM_VSU0_16FLOP
#
#PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|2|*|+|N2|4|*|+|N3|8|*|+|,PM_VSU_1FLOP,PM_VSU_2FLOP,PM_VSU_4FLOP,PM_VSU_8FLOP
PRESET,PAPI_FP_OPS,NOT_DERIVED,PM_FLOP
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN
PRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1
PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN
#PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN
PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER8
CPU,power8
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1,PM_ST_MISS_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1
PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1
PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
#n/aPRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS
#n/aPRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
#n/aPRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
#n/aPRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
#n/aPRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
#n/aPRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS
#n/aPRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
#n/aPRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
#n/aPRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS
#n/aPRESET,PAPI_FMA_INS,NOT_DERIVED,PM_VSU_FMA
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
#n/aPRESET,PAPI_INT_INS,DERIVED_ADD,PM_FXU0_FIN,PM_FXU1_FIN
PRESET,PAPI_FP_OPS,NOT_DERIVED,PM_FLOP
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|4|*|N1|8|*|N2|16|*|N3|32|*|+|+|+|,PM_VSU0_2FLOP,PM_VSU0_4FLOP,PM_VSU0_8FLOP,PM_VSU0_16FLOP
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|4|*|N1|8|*|N2|16|*|N3|32|*|+|+|+|,PM_VSU0_2FLOP,PM_VSU0_4FLOP,PM_VSU0_8FLOP,PM_VSU0_16FLOP
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN
#n/aPRESET,PAPI_LD_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1
#/naPRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN
#PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_CMPL
PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED_CMPL
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED_BR_CMPL
PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_TAKEN_CMPL
PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND_CMPL
#n/aPRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER9
CPU,power9
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_LD_MISS_L1_ALT,PM_ST_MISS_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_LD_MISS_L1_ALT
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1
PRESET,PAPI_L1_DCR,DERIVED_SUB,PM_LD_REF_L1,PM_LD_MISS_L1_ALT
#PRESET,PAPI_L1_DCA,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-,PM_ST_FIN,PM_ST_MISS_L1,PM_LD_REF_L1,PM_LD_MISS_L1_ALT
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_CMPL
PRESET,PAPI_L2_DCM,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,PM_L2_LD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,PM_L2_ST_MISS
PRESET,PAPI_L2_DCR,NOT_DERIVED,PM_DATA_FROM_L2
PRESET,PAPI_L2_DCW,NOT_DERIVED,PM_L2_ST_HIT
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L2MISS
PRESET,PAPI_L3_DCM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PM_DATA_FROM_LMEM,PM_DATA_FROM_RMEM
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_L2_INST_MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FMA_CMPL
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_FIN
# Note: PAPI_FP_OPS is not available on this architecture. The following combination is
# equivalent to all FLOPs; however, these events cannot be added to the same event set.
# If a user chooses, they can utilize the multiplexing feature with these events.
# 8 * PM_8FLOP_CMPL + 4 * PM_4FLOP_CMPL + 2 * PM_2FLOP_CMPL + 1 * PM_1FLOP_CMPL
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP_CMPL
PRESET,PAPI_DP_OPS,NOT_DERIVED,PM_DP_QP_FLOP_CMPL
PRESET,PAPI_SP_OPS,NOT_DERIVED,PM_SP_FLOP_CMPL
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_FIN
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_REF_L1
PRESET,PAPI_LST_INS,NOT_DERIVED,PM_LSU_FIN
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_REF_L1,PM_LD_MISS_L1,PM_ST_FIN
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BRU_FIN
PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_TAKEN_BR_MPRED_CMPL
PRESET,PAPI_BR_PRC,NOT_DERIVED,PM_BR_PRED
PRESET,PAPI_BR_CN,DERIVED_SUB,PM_BR_CMPL,PM_BR_UNCOND
PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|,PM_BR_CMPL,PM_BR_TAKEN_CMPL
PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_UNCOND
PRESET,PAPI_BR_TKN,NOT_DERIVED,PM_BR_CORECT_PRED_TAKEN_CMPL
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PM_FXU_IDLE
#
CPU,POWER10
CPU,power10
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,PM_DATA_FROM_L1MISS,PM_ST_MISS_L1
PRESET,PAPI_L1_LDM,NOT_DERIVED,PM_DATA_FROM_L1MISS
PRESET,PAPI_L1_STM,NOT_DERIVED,PM_ST_MISS_L1
PRESET,PAPI_L1_DCW,DERIVED_SUB,PM_ST_FIN,PM_ST_MISS_L1
PRESET,PAPI_L1_DCR,NOT_DERIVED,PM_LD_HIT_L1
PRESET,PAPI_L1_DCA,DERIVED_ADD,PM_LD_REF_L1,PM_ST_CMPL
PRESET,PAPI_L2_DCM,DERIVED_POSTFIX,N0|N1|2|*|+|,PM_DATA_FROM_L2MISS,PM_L2_ST_MISS
PRESET,PAPI_L2_LDM,DERIVED_POSTFIX,N0|2|*|,PM_L2_LD_MISS
PRESET,PAPI_L2_STM,DERIVED_POSTFIX,N0|2|*|,PM_L2_ST_MISS
PRESET,PAPI_L2_DCR,NOT_DERIVED,PM_DATA_FROM_L2
PRESET,PAPI_L2_DCW,DERIVED_POSTFIX,N0|2|*|,PM_L2_ST_HIT
PRESET,PAPI_L3_DCR,NOT_DERIVED,PM_DATA_FROM_L3
PRESET,PAPI_L3_DCM,NOT_DERIVED,PM_DATA_FROM_L3MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,PM_DATA_FROM_L3MISS
PRESET,PAPI_L1_ICH,NOT_DERIVED,PM_INST_FROM_L1
PRESET,PAPI_L1_ICM,NOT_DERIVED,PM_L1_ICACHE_MISS
PRESET,PAPI_L2_ICM,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L2_ICH,NOT_DERIVED,PM_INST_FROM_L2
PRESET,PAPI_L3_ICA,NOT_DERIVED,PM_INST_FROM_L2MISS
PRESET,PAPI_L3_ICH,NOT_DERIVED,PM_INST_FROM_L3
PRESET,PAPI_L3_ICM,NOT_DERIVED,PM_INST_FROM_L3MISS
PRESET,PAPI_FMA_INS,NOT_DERIVED,PM_FMA_CMPL
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PM_INST_DISP
PRESET,PAPI_TOT_INS,NOT_DERIVED,PM_INST_CMPL
PRESET,PAPI_INT_INS,NOT_DERIVED,PM_FXU_ISSUE
# Note: PAPI_FP_OPS is not available on this architecture. The following combination is
# equivalent to all FLOPs; however, these events cannot be added to the same event set.
# If a user chooses, they can utilize the multiplexing feature with these events.
# 8 * PM_8FLOP_CMPL + 4 * PM_4FLOP_CMPL + 2 * PM_2FLOP_CMPL + 1 * PM_1FLOP_CMPL
PRESET,PAPI_FP_INS,NOT_DERIVED,PM_FLOP_CMPL
PRESET,PAPI_DP_OPS,NOT_DERIVED,PM_DPP_FLOP_CMPL
PRESET,PAPI_SP_OPS,NOT_DERIVED,PM_SP_FLOP_CMPL
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PM_RUN_CYC
PRESET,PAPI_HW_INT,NOT_DERIVED,PM_EXT_INT
PRESET,PAPI_STL_ICY,DERIVED_POSTFIX,N0|N1|-|,PM_RUN_CYC,PM_1PLUS_PPC_DISP
PRESET,PAPI_SR_INS,NOT_DERIVED,PM_ST_CMPL
PRESET,PAPI_LD_INS,NOT_DERIVED,PM_LD_CMPL
PRESET,PAPI_LST_INS,DERIVED_ADD,PM_LD_CMPL,PM_ST_CMPL
PRESET,PAPI_BR_INS,NOT_DERIVED,PM_BR_CMPL
PRESET,PAPI_BR_MSP,NOT_DERIVED,PM_BR_MPRED_CMPL
PRESET,PAPI_BR_PRC,DERIVED_ADD,PM_PRED_BR_TKN_COND_DIR,PM_PRED_BR_NTKN_COND_DIR
PRESET,PAPI_BR_CN,NOT_DERIVED,PM_BR_COND_CMPL
PRESET,PAPI_BR_NTK,DERIVED_SUB,PM_BR_FIN,PM_BR_TKN_FIN
PRESET,PAPI_BR_UCN,NOT_DERIVED,PM_BR_TKN_UNCOND_FIN
PRESET,PAPI_BR_TKN,DERIVED_SUB,PM_BR_TKN_FIN,PM_BR_TKN_UNCOND_FIN
#
CPU,ultra12
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT
PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS
PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF
PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR
PRESET,PAPI_MEM_RCY,NOT_DERIVED,LOAD_USE
PRESET,PAPI_L2_TCA,NOT_DERIVED,EC_REF
PRESET,PAPI_BR_MSP,NOT_DERIVED,DISPATCH0_MISPRED
PRESET,PAPI_L1_ICH,NOT_DERIVED,IC_HIT
PRESET,PAPI_L2_TCH,NOT_DERIVED,EC_HIT
PRESET,PAPI_L2_TCM,DERIVED_SUB,EC_REF,EC_HIT
#
CPU,ultra3
CPU,ultra3i
CPU,ultra3+
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT
PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS
PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF
PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR
PRESET,PAPI_L2_TCA,NOT_DERIVED,EC_REF
PRESET,PAPI_BR_TKN,NOT_DERIVED,IU_STAT_BR_COUNT_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,IU_STAT_BR_COUNT_UNTAKEN
PRESET,PAPI_BR_MSP,DERIVED_ADD,IU_STAT_BR_MISS_TAKEN,IU_STAT_BR_MISS_UNTAKEN
PRESET,PAPI_BR_INS,DERIVED_ADD,IU_STAT_BR_COUNT_TAKEN,IU_STAT_BR_COUNT_UNTAKEN
PRESET,PAPI_L2_TCM,NOT_DERIVED,EC_MISSES
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
#
CPU,ultra4+
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLE_CNT
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT
PRESET,PAPI_L1_ICM,NOT_DERIVED,DISPATCH0_IC_MISS
PRESET,PAPI_L1_ICA,NOT_DERIVED,IC_REF
PRESET,PAPI_L1_DCR,NOT_DERIVED,DC_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,DC_WR
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_REF
PRESET,PAPI_BR_TKN,NOT_DERIVED,IU_STAT_BR_COUNT_TAKEN
PRESET,PAPI_BR_NTK,NOT_DERIVED,IU_STAT_BR_COUNT_UNTAKEN
PRESET,PAPI_BR_MSP,DERIVED_ADD,IU_STAT_BR_MISS_TAKEN,IU_STAT_BR_MISS_UNTAKEN
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_L3_TCM,NOT_DERIVED,L3_MISS
#
CPU,niagara
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_CNT
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_INSTR_CNT
PRESET,PAPI_L1_ICM,NOT_DERIVED,IC_MISS
PRESET,PAPI_L1_DCM,NOT_DERIVED,DC_MISS
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
#
CPU,niagara2
#
CPU,Cell
#
PRESET,PAPI_TOT_INS,DERIVED_POSTFIX,N0|N1|+|2|*|,PPC_INST_COMMIT_TH0,PPC_INST_COMMIT_TH1
#PRESET,PAPI_L1_DCM,DERIVED_ADD,L1_DCACHE_MISS_TH0,L1_DCACHE_MISS_TH1 where's TH1??
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1_DCACHE_MISS_TH0
PRESET,PAPI_L2_TCH,NOT_DERIVED,L2_CACHE_HIT
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_LD_MISS
PRESET,PAPI_L2_STM,NOT_DERIVED,L2_ST_MISS
PRESET,PAPI_BR_MSP,DERIVED_ADD,BRANCH_FLUSH_TH0,BRANCH_FLUSH_TH1
PRESET,PAPI_BR_INS,DERIVED_ADD,BRANCH_COMMIT_TH0,BRANCH_COMMIT_TH1
#
CPU,arm_1176
#
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE_MISS
PRESET,PAPI_STL_ICY,NOT_DERIVED,IBUF_STALL
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_MISS
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_EXEC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MISPREDICT
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXEC
PRESET,PAPI_L1_DCH,NOT_DERIVED,DCACHE_HIT
PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS
PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_MISS
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
#
CPU,arm_ac7
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_READS
PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_WRITES
PRESET,PAPI_HW_INT,NOT_DERIVED,EXCEPTION_TAKEN
PRESET,PAPI_BR_INS,NOT_DERIVED,SW_CHANGE_PC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_MEM_ACCESS
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_TCM,NOT_DERIVED,EXTERNAL_MEMORY_REQUEST
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1D_TLB_REFILL
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
#
CPU,arm_ac8
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXECUTED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE
PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED
PRESET,PAPI_LD_INS,NOT_DERIVED,DREAD
PRESET,PAPI_SR_INS,NOT_DERIVED,DWRITE
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL
PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS
PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1_INST
PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_ACCESS
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISS
PRESET,PAPI_BR_TKN,NOT_DERIVED,PC_BRANCH_EXECUTED
PRESET,PAPI_STL_ICY,NOT_DERIVED,CYCLES_INST_STALL
#
CPU,arm_ac9
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_OUT_OF_RENAME_STAGE
PRESET,PAPI_TOT_IIS,NOT_DERIVED,MAIN_UNIT_EXECUTED_INST
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_HW_INT,NOT_DERIVED,EXT_INTERRUPTS
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_EXECUTED_INST
PRESET,PAPI_VEC_INS,NOT_DERIVED,NEON_EXECUTED_INST
PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE
PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED
PRESET,PAPI_LD_INS,NOT_DERIVED,DREAD
PRESET,PAPI_SR_INS,NOT_DERIVED,DWRITE
PRESET,PAPI_TLB_IM,NOT_DERIVED,ITLB_MISS
PRESET,PAPI_TLB_DM,NOT_DERIVED,DTLB_REFILL
PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESS
PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,IFETCH_MISS
#
CPU,arm_ac15
CPU,arm_ac57
CPU,arm_ac72
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_IIS,NOT_DERIVED,INST_SPEC_EXEC
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP
PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD
PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS
PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS
PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS
PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_READ_REFILL,L1D_WRITE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL

#####################
# ARM Cortex A53    #
#####################
# These are based entirely on libpfm4 event table
# They have not been tested on real hardware
CPU,arm_ac53
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCH_PRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE_ACCESS
PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL
PRESET,PAPI_TLB_DM,NOT_DERIVED,L1D_TLB_REFILL
PRESET,PAPI_HW_INT,NOT_DERIVED,EXCEPTION_TAKEN

#
CPU,arm_ac76
#
PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L3_DCM,NOT_DERIVED,L3D_CACHE_REFILL
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1I_CACHE_REFILL,L1D_CACHE_REFILL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L3_TCM,NOT_DERIVED,L3D_CACHE_REFILL
PRESET,PAPI_L3_LDM,NOT_DERIVED,LL_CACHE_MISS_RD
PRESET,PAPI_L3_STM,DERIVED_SUB,L3D_CACHE_REFILL,LL_CACHE_MISS_RD
PRESET,PAPI_TLB_DM,DERIVED_ADD,L1D_TLB_REFILL,L2D_TLB_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL 
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1I_TLB_REFILL,L1D_TLB_REFILL,L2D_TLB_REFILL
PRESET,PAPI_L1_LDM,NOT_DERIVED,L1D_CACHE_REFILL_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L1D_CACHE_REFILL_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_CACHE_REFILL_WR
PRESET,PAPI_L3_DCH,DERIVED_SUB,L3D_CACHE,L3D_CACHE_REFILL
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_INT_INS,NOT_DERIVED,DP_SPEC
PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
PRESET,PAPI_L2_DCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L2_DCA,DERIVED_SUB,L2D_CACHE,L2D_CACHE_RD
#PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_DCA,NOT_DERIVED,L3D_CACHE
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_DCR,NOT_DERIVED,L3D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,|N0|N1|+|N2|-|N3|-|,L1D_CACHE,L1I_CACHE,L1I_CACHE_REFILL,L1D_CACHE_REFILL
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L3_TCH,DERIVED_SUB,LL_CACHE_RD,LL_CACHE_MISS_RD
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1I_CACHE,L1D_CACHE
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_TCA,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_TCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_TCR,NOT_DERIVED,L3_CACHE_RD
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_TCW,DERIVED_SUB,L3D_CACHE,L3_CACHE_RD


#
CPU,qcom_krait
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTR_EXECUTED
PRESET,PAPI_TOT_IIS,NOT_DERIVED,INSTR_EXECUTED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_BR_INS,NOT_DERIVED,PC_WRITE
PRESET,PAPI_BR_MSP,NOT_DERIVED,PC_BRANCH_MIS_PRED
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE_ACCESS
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
# Will be supported eventually
#PRESET,PAPI_L1_ICA,NOT_DERIVED,KRAIT_L1_ICACHE_ACCESS
#PRESET,PAPI_L1_ICM,NOT_DERIVED,KRAIT_L1_ICACHE_MISS
#
CPU,arm_xgene
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,INST_SPEC_EXEC_VFP
PRESET,PAPI_VEC_INS,NOT_DERIVED,INST_SPEC_EXEC_SIMD
PRESET,PAPI_BR_INS,NOT_DERIVED,INST_SPEC_EXEC_SOFT_PC
PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCH_MISPRED
PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_MEM_READ_ACCESS
PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_MEM_WRITE_ACCESS
PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_READ_ACCESS,L1D_WRITE_ACCESS
PRESET,PAPI_L1_DCM,DERIVED_ADD,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_READ_ACCESS
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_WRITE_ACCESS
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE_ACCESS
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_READ_ACCESS
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_WRITE_ACCESS
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_READ_REFILL
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_WRITE_REFILL

#####################
# ARM ThunderX2     #
#####################
CPU,arm_thunderx2
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_RETIRED
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_RETIRED
PRESET,PAPI_L1_DCA,DERIVED_ADD,L1D_CACHE_RD,L1D_CACHE_WR
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCH,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD

#########################
# ARM Fujitsu A64FX     #
#########################
CPU,arm_a64fx
#
PRESET,PAPI_PRF_DM,DERIVED_SUB,L2D_CACHE_REFILL_PRF,L2D_CACHE_MIBMCH_PRF
PRESET,PAPI_MEM_SCY,NOT_DERIVED,LD_COMP_WAIT_L2_MISS
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_STL_CCY,NOT_DERIVED,0INST_COMMIT
PRESET,PAPI_FUL_CCY,DERIVED_SUB,CPU_CYCLES,0INST_COMMIT,1INST_COMMIT,2INST_COMMIT,3INST_COMMIT
PRESET,PAPI_BRU_IDL,NOT_DERIVED,BR_COMP_WAIT
PRESET,PAPI_FXU_IDL,DERIVED_SUB,EU_COMP_WAIT,FL_COMP_WAIT
PRESET,PAPI_FPU_IDL,NOT_DERIVED,FL_COMP_WAIT
PRESET,PAPI_LSU_IDL,NOT_DERIVED,LD_COMP_WAIT
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_FMA_INS,NOT_DERIVED,FP_FMA_SPEC
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_SPEC
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_LST_INS,NOT_DERIVED,LDST_SPEC
PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC
#PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
#PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
#PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
#PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L2_DCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|+|,L2D_CACHE,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF
PRESET,PAPI_L2_DCM,DERIVED_SUB,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L2_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|+|,L2D_CACHE,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF
PRESET,PAPI_L2_TCM,DERIVED_SUB,L2D_CACHE_REFILL,L2D_SWAP_DM,L2D_CACHE_MIBMCH_PRF
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L2I_TLB_REFILL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L2D_TLB_REFILL,L2I_TLB_REFILL
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SP_SCALE_OPS_SPEC,FP_SP_FIXED_OPS_SPEC
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_DP_SCALE_OPS_SPEC,FP_DP_FIXED_OPS_SPEC

#########################
# ARM Neoverse N1       #
#########################
CPU,arm_n1
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
PRESET,PAPI_VEC_INS,NOT_DERIVED,ASE_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL

#########################
# ARM Neoverse N2       #
#########################
CPU,arm_n2
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL

#########################
# ARM Neoverse V1       #
#########################
CPU,arm_v1
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_FP_INS,NOT_DERIVED,VFP_SPEC
PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE_ACCESS
PRESET,PAPI_L2_DCA,DERIVED_ADD,L2D_CACHE_RD,L2D_CACHE_WR
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL

cuda,GH100
cuda,GA100
#
PRESET,PAPI_CUDA_FP16_FMA,NOT_DERIVED,cuda:::sm__sass_thread_inst_executed_op_hfma_pred_on:stat=sum
PRESET,PAPI_CUDA_BF16_FMA,NOT_DERIVED,cuda:::sm__sass_thread_inst_executed_op_hfma_pred_on:stat=sum
PRESET,PAPI_CUDA_FP32_FMA,NOT_DERIVED,cuda:::sm__sass_thread_inst_executed_op_ffma_pred_on:stat=sum
PRESET,PAPI_CUDA_FP64_FMA,NOT_DERIVED,cuda:::sm__sass_thread_inst_executed_op_dfma_pred_on:stat=sum
PRESET,PAPI_CUDA_FP_FMA,DERIVED_POSTFIX,N0|N1|+|N2|+|,cuda:::sm__sass_thread_inst_executed_op_hfma_pred_on:stat=sum,cuda:::sm__sass_thread_inst_executed_op_ffma_pred_on:stat=sum,cuda:::sm__sass_thread_inst_executed_op_dfma_pred_on:stat=sum
cuda,GH100
PRESET,PAPI_CUDA_FP8_OPS,NOT_DERIVED,cuda:::sm__ops_path_tensor_src_fp8:stat=sum

#########################
# ARM Neoverse V2       #
#########################
CPU,arm_v2
#
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_INT_INS,NOT_DERIVED,DP_SPEC
#NOT_IMPLEMENTED,PAPI_TOT_IIS,Instructions issued
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_REF_CYC,NOT_DERIVED,CNT_CYCLES
PRESET,PAPI_STL_CCY,NOT_DERIVED,STALL
#NOT_IMPLEMENTED,PAPI_FUL_CCY,Cycles with maximum instructions completed
#NOT_IMPLEMENTED,PAPI_FUL_ICY,Cycles with maximum instruction issue
#NOT_IMPLEMENTED,PAPI_FXU_IDL,Cycles integer units are idle
#NOT_IMPLEMENTED,PAPI_LSU_IDL,Cycles load/store units are idle
#NOT_IMPLEMENTED,PAPI_MEM_RCY,Cycles Stalled Waiting for memory Reads
#NOT_IMPLEMENTED,PAPI_MEM_SCY,Cycles Stalled Waiting for memory accesses
#NOT_IMPLEMENTED,PAPI_MEM_WCY,Cycles Stalled Waiting for memory writes
#NOT_IMPLEMENTED,PAPI_FP_STAL,Cycles the FP unit(s) are stalled
#NOT_IMPLEMENTED,PAPI_FPU_IDL,Cycles floating point units are idle
#NOT_IMPLEMENTED,PAPI_BRU_IDL,Cycles branch units are idle
PRESET,PAPI_STL_ICY,NOT_DERIVED,STALL
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_FP_OPS,DERIVED_ADD,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC
#NOT_IMPLEMENTED,PAPI_SP_OPS,Floating point operations; optimized to count scaled single precision vector operations
#NOT_IMPLEMENTED,PAPI_DP_OPS,Floating point operations; optimized to count scaled double precision vector operations
PRESET,PAPI_FP_INS,DERIVED_ADD,FP_HP_SPEC,FP_SP_SPEC,FP_DP_SPEC
#NOT_IMPLEMENTED,PAPI_FAD_INS,Floating point add instructions
#NOT_IMPLEMENTED,PAPI_FDV_INS,Floating point divide instructions
#NOT_IMPLEMENTED,PAPI_FMA_INS,FMA instructions completed
#NOT_IMPLEMENTED,PAPI_FML_INS,Floating point multiply instructions
#NOT_IMPLEMENTED,PAPI_FNV_INS,Floating point inverse instructions
#NOT_IMPLEMENTED,PAPI_FSQ_INS,Floating point square root instructions
PRESET,PAPI_VEC_INS,DERIVED_ADD,SVE_INST_SPEC,ASE_INST_SPEC
#NOT_IMPLEMENTED,PAPI_VEC_DP,Double precision vector/SIMD instructions
#NOT_IMPLEMENTED,PAPI_VEC_SP,Single precision vector/SIMD instructions
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_RETIRED
#NOT_IMPLEMENTED,PAPI_BR_CN,Conditional branch instructions
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_RETIRED,BR_MIS_PRED_RETIRED
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED_RETIRED
#NOT_IMPLEMENTED,PAPI_BR_NTK,Conditional branch instructions not taken
#NOT_IMPLEMENTED,PAPI_BR_TKN,Conditional branch instructions taken
#NOT_IMPLEMENTED,PAPI_BR_UCN,Unconditional branch instructions
#NOT_IMPLEMENTED,PAPI_BTAC_M,Branch target address cache misses
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_LST_INS,DERIVED_ADD,LD_SPEC,ST_SPEC
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
#NOT_IMPLEMENTED,PAPI_L1_ICR,Level 1 instruction cache reads
#NOT_IMPLEMENTED,PAPI_L1_ICW,Level 1 instruction cache writes
#NOT_IMPLEMENTED,PAPI_L1_LDM,Level 1 load misses
#NOT_IMPLEMENTED,PAPI_L1_STM,Level 1 store misses
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
#NOT_IMPLEMENTED,PAPI_L1_TCR,Level 1 total cache reads
#NOT_IMPLEMENTED,PAPI_L1_TCW,Level 1 total cache writes
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L2_DCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_RD
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_CACHE_REFILL_WR
#NOT_IMPLEMENTED,PAPI_L2_ICA,Level 2 instruction cache accesses
#NOT_IMPLEMENTED,PAPI_L2_ICH,Level 2 instruction cache hits
#NOT_IMPLEMENTED,PAPI_L2_ICM,Level 2 instruction cache misses
#NOT_IMPLEMENTED,PAPI_L2_ICR,Level 2 instruction cache reads
#NOT_IMPLEMENTED,PAPI_L2_ICW,Level 2 instruction cache writes
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2D_CACHE_REFILL
PRESET,PAPI_L2_TCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_TCA,NOT_DERIVED,L3D_CACHE
PRESET,PAPI_L3_DCA,NOT_DERIVED,L3D_CACHE
#NOT_IMPLEMENTED,PAPI_L3_DCH,Level 3 data cache hits
PRESET,PAPI_L3_DCM,NOT_DERIVED,L3D_CACHE_REFILL
#NOT_IMPLEMENTED,PAPI_L3_DCR,Level 3 data cache reads
#NOT_IMPLEMENTED,PAPI_L3_DCW,Level 3 data cache writes
#NOT_IMPLEMENTED,PAPI_L3_ICA,Level 3 instruction cache accesses
#NOT_IMPLEMENTED,PAPI_L3_ICH,Level 3 instruction cache hits
#NOT_IMPLEMENTED,PAPI_L3_ICM,Level 3 instruction cache misses
#NOT_IMPLEMENTED,PAPI_L3_ICR,Level 3 instruction cache reads
#NOT_IMPLEMENTED,PAPI_L3_ICW,Level 3 instruction cache writes
#NOT_IMPLEMENTED,PAPI_L3_LDM,Level 3 load misses
#NOT_IMPLEMENTED,PAPI_L3_STM,Level 3 store misses
#NOT_IMPLEMENTED,PAPI_L3_TCH,Level 3 total cache hits
#NOT_IMPLEMENTED,PAPI_L3_TCM,Level 3 cache misses
#NOT_IMPLEMENTED,PAPI_L3_TCR,Level 3 total cache reads
#NOT_IMPLEMENTED,PAPI_L3_TCW,Level 3 total cache writes
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_SYC_INS,DERIVED_ADD,ISB_SPEC,DSB_SPEC,DMB_SPEC
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L1I_TLB_REFILL
#NOT_IMPLEMENTED,PAPI_TLB_SD,Translation lookaside buffer shootdowns
PRESET,PAPI_TLB_TL,DERIVED_ADD,L1D_TLB_REFILL,L2D_TLB_REFILL
#NOT_IMPLEMENTED,PAPI_CA_CLN,Requests for exclusive access to clean cache line
#NOT_IMPLEMENTED,PAPI_CA_INV,Requests for cache line invalidation
#NOT_IMPLEMENTED,PAPI_CA_ITV,Requests for cache line intervention
#NOT_IMPLEMENTED,PAPI_CA_SHR,Requests for exclusive access to shared cache line
#NOT_IMPLEMENTED,PAPI_CA_SNP,Requests for a snoop
#NOT_IMPLEMENTED,PAPI_CSR_FAL,Failed store conditional instructions
#NOT_IMPLEMENTED,PAPI_CSR_SUC,Successful store conditional instructions
#NOT_IMPLEMENTED,PAPI_CSR_TOT,Total store conditional instructions
#NOT_IMPLEMENTED,PAPI_PRF_DM,Data prefetch cache misses

##############################
# ARM Fujitsu FUJITSU-MONAKA #
##############################
CPU,arm_monaka
#
PRESET,PAPI_L1_DCM,NOT_DERIVED,L1D_CACHE_REFILL
PRESET,PAPI_L1_ICM,NOT_DERIVED,L1I_CACHE_REFILL
PRESET,PAPI_L2_DCM,NOT_DERIVED,L2D_CACHE_REFILL
#PRESET,PAPI_L3_DCM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS
PRESET,PAPI_L1_TCM,DERIVED_ADD,L1D_CACHE_REFILL,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2D_CACHE_REFILL
#PRESET,PAPI_L3_TCM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS
PRESET,PAPI_L3_LDM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_DM_RD
PRESET,PAPI_L3_STM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_DM_WR
PRESET,PAPI_BRU_IDL,NOT_DERIVED,BR_COMP_WAIT
PRESET,PAPI_FXU_IDL,DERIVED_SUB,EU_COMP_WAIT,FL_COMP_WAIT
PRESET,PAPI_FPU_IDL,NOT_DERIVED,FL_COMP_WAIT
PRESET,PAPI_LSU_IDL,NOT_DERIVED,LD_COMP_WAIT
PRESET,PAPI_TLB_DM,NOT_DERIVED,L2D_TLB_REFILL
PRESET,PAPI_TLB_IM,NOT_DERIVED,L2I_TLB_REFILL
PRESET,PAPI_TLB_TL,DERIVED_ADD,L2D_TLB_REFILL,L2I_TLB_REFILL
PRESET,PAPI_L1_LDM,DERIVED_ADD,L1D_CACHE_REFILL_DM_RD,L1I_CACHE_REFILL_DM_RD
PRESET,PAPI_L1_STM,NOT_DERIVED,L1D_CACHE_REFILL_DM_WR
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2D_CACHE_REFILL_DM_RD
PRESET,PAPI_L2_STM,NOT_DERIVED,L2D_CACHE_REFILL_DM_WR
#RESET,PAPI_PRF_DM,NOT_DERIVED,L2D_CACHE_REFILL_L3D_MISS_PRF
#PRESET,PAPI_L3_DCH,NOT_DERIVED,L2D_CACHE_REFILL_L3D_HIT
PRESET,PAPI_MEM_SCY,DERIVED_ADD,STALL_FRONTEND_MEMBOUND,STALL_BACKEND_MEMBOUND
PRESET,PAPI_STL_ICY,DERIVED_ADD,STALL_FRONTEND,STALL_BACKEND
PRESET,PAPI_STL_CCY,NOT_DERIVED,_0INST_COMMIT
PRESET,PAPI_FUL_CCY,DERIVED_POSTFIX,N0|N1|-|N2|-|N3|-|N4|-|N5|-|,CPU_CYCLES,_0INST_COMMIT,_1INST_COMMIT,_2INST_COMMIT,_3INST_COMMIT,_4INST_COMMIT
PRESET,PAPI_HW_INT,DERIVED_ADD,EXC_IRQ,EXC_FIQ
PRESET,PAPI_BR_MSP,NOT_DERIVED,BR_MIS_PRED
PRESET,PAPI_BR_PRC,DERIVED_SUB,BR_PRED,BR_MIS_PRED
PRESET,PAPI_FMA_INS,NOT_DERIVED,FP_FMA_SPEC
PRESET,PAPI_TOT_INS,NOT_DERIVED,INST_RETIRED
PRESET,PAPI_INT_INS,NOT_DERIVED,INT_SPEC
PRESET,PAPI_FP_INS,NOT_DERIVED,FP_SPEC
PRESET,PAPI_LD_INS,NOT_DERIVED,LD_SPEC
PRESET,PAPI_SR_INS,NOT_DERIVED,ST_SPEC
PRESET,PAPI_BR_INS,NOT_DERIVED,BR_PRED
PRESET,PAPI_VEC_INS,NOT_DERIVED,SIMD_INST_RETIRED
PRESET,PAPI_RES_STL,NOT_DERIVED,STALL_BACKEND
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_LST_INS,NOT_DERIVED,LDST_SPEC
PRESET,PAPI_SYC_INS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|,ISB_SPEC,DSB_SPEC,DMB_SPEC,CSDB_SPEC
PRESET,PAPI_L1_DCH,DERIVED_SUB,L1D_CACHE,L1D_CACHE_REFILL
PRESET,PAPI_L2_DCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
PRESET,PAPI_L1_DCA,NOT_DERIVED,L1D_CACHE
PRESET,PAPI_L2_DCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_DCA,NOT_DERIVED,L2D_CACHE_REFILL_L3D_CACHE
PRESET,PAPI_L1_DCR,NOT_DERIVED,L1D_CACHE_RD
PRESET,PAPI_L2_DCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_DCR,NOT_DERIVED,L3D_CACHE_RD
PRESET,PAPI_L1_DCW,NOT_DERIVED,L1D_CACHE_WR
PRESET,PAPI_L2_DCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_DCW,DERIVED_SUB,L2D_CACHE_REFILL_L3D_CACHE,L3D_CACHE_RD
PRESET,PAPI_L1_ICH,DERIVED_SUB,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L1_ICA,NOT_DERIVED,L1I_CACHE
PRESET,PAPI_L1_TCH,DERIVED_POSTFIX,N0|N1|-|N2|+|N3|-|,L1D_CACHE,L1D_CACHE_REFILL,L1I_CACHE,L1I_CACHE_REFILL
PRESET,PAPI_L2_TCH,DERIVED_SUB,L2D_CACHE,L2D_CACHE_REFILL
#PRESET,PAPI_L3_TCH,NOT_DERIVED,L2D_CACHE_REFILL_L3D_HIT
PRESET,PAPI_L1_TCA,DERIVED_ADD,L1D_CACHE,L1I_CACHE
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2D_CACHE
PRESET,PAPI_L3_TCA,NOT_DERIVED,L2D_CACHE_REFILL_L3D_CACHE
PRESET,PAPI_L2_TCR,NOT_DERIVED,L2D_CACHE_RD
PRESET,PAPI_L3_TCR,NOT_DERIVED,L3D_CACHE_RD
PRESET,PAPI_L2_TCW,NOT_DERIVED,L2D_CACHE_WR
PRESET,PAPI_L3_TCW,DERIVED_SUB,L2D_CACHE_REFILL_L3D_CACHE,L3D_CACHE_RD
PRESET,PAPI_FML_INS,NOT_DERIVED,FP_MUL_SPEC
PRESET,PAPI_FDV_INS,NOT_DERIVED,FP_DIV_SPEC
PRESET,PAPI_FSQ_INS,NOT_DERIVED,FP_SQRT_SPEC
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SCALE_OPS_SPEC,FP_FIXED_OPS_SPEC
PRESET,PAPI_SP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_SP_SCALE_OPS_SPEC,FP_SP_FIXED_OPS_SPEC
PRESET,PAPI_DP_OPS,DERIVED_POSTFIX,N0|512|128|/|*|N1|+|,FP_DP_SCALE_OPS_SPEC,FP_DP_FIXED_OPS_SPEC
PRESET,PAPI_VEC_SP,NOT_DERIVED,ASE_SVE_FP_SP_SPEC
PRESET,PAPI_VEC_DP,NOT_DERIVED,ASE_SVE_FP_DP_SPEC
PRESET,PAPI_REF_CYC,NOT_DERIVED,CNT_CYCLES

#
CPU,mips_74k
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS
PRESET,PAPI_L1_ICA,NOT_DERIVED,ICACHE_ACCESSES
PRESET,PAPI_L1_ICM,NOT_DERIVED,ICACHE_MISSES
PRESET,PAPI_L1_DCA,NOT_DERIVED,DCACHE_ACCESSES
PRESET,PAPI_L1_DCM,NOT_DERIVED,DCACHE_MISSES
PRESET,PAPI_L1_TCA,DERIVED_ADD,DCACHE_ACCESSES,ICACHE_ACCESSES
PRESET,PAPI_L1_TCM,DERIVED_ADD,ICACHE_MISSES,DCACHE_MISSES
PRESET,PAPI_L2_TCA,NOT_DERIVED,L2_CACHE_ACCESSES
PRESET,PAPI_L2_TCM,NOT_DERIVED,L2_CACHE_MISSES
PRESET,PAPI_FP_INS,NOT_DERIVED,FPU_INSNS
PRESET,PAPI_INT_INS,NOT_DERIVED,INTEGER_INSNS
PRESET,PAPI_LD_INS,NOT_DERIVED,LOAD_INSNS
PRESET,PAPI_SR_INS,NOT_DERIVED,STORE_INSNS
PRESET,PAPI_TLB_IM,NOT_DERIVED,JTLB_INSN_MISSES
PRESET,PAPI_TLB_DM,NOT_DERIVED,JTLB_DATA_MISSES
PRESET,PAPI_BR_CN,NOT_DERIVED,COND_BRANCH_INSNS
PRESET,PAPI_BR_MSP,NOT_DERIVED,MISPREDICTED_BRANCH_INSNS
PRESET,PAPI_CSR_FAL,NOT_DERIVED,FAILED_SC_INSNS
PRESET,PAPI_CSR_TOT,NOT_DERIVED,SC_INSNS
PRESET,PAPI_FUL_ICY,NOT_DERIVED,DUAL_ISSUE_CYCLES
PRESET,PAPI_STL_CCY,NOT_DERIVED,NO_INSN_CYCLES
PRESET,PAPI_FUL_CCY,NOT_DERIVED,TWO_INSNS_CYCLES
#
CPU,MIPSICE9A
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC
PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD
PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE
PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL
PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC
PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FLOAT
PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH
PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS
PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP
PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS
PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS
PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS
PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL
PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL
#
CPU,MIPSICE9B
#
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CYCLES
PRESET,PAPI_TOT_INS,NOT_DERIVED,CPU_INSEXEC
PRESET,PAPI_L1_ICA,NOT_DERIVED,CPU_INSFETCH
PRESET,PAPI_LD_INS,NOT_DERIVED,CPU_LOAD
PRESET,PAPI_SR_INS,NOT_DERIVED,CPU_STORE
PRESET,PAPI_CSR_FAL,NOT_DERIVED,CPU_SCFAIL
PRESET,PAPI_CSR_TOT,NOT_DERIVED,CPU_SC
PRESET,PAPI_FP_INS,NOT_DERIVED,CPU_FPARITH
PRESET,PAPI_BR_INS,NOT_DERIVED,CPU_BRANCH
PRESET,PAPI_TLB_IM,NOT_DERIVED,CPU_ITLBMISS
PRESET,PAPI_TLB_TL,NOT_DERIVED,CPU_TLBTRAP
PRESET,PAPI_TLB_DM,NOT_DERIVED,CPU_DTLBMISS
PRESET,PAPI_BR_MSP,NOT_DERIVED,CPU_MISPRED
PRESET,PAPI_L1_ICM,NOT_DERIVED,CPU_ICMISS
PRESET,PAPI_L1_DCM,NOT_DERIVED,CPU_DCMISS
PRESET,PAPI_MEM_SCY,NOT_DERIVED,CPU_MSTALL
PRESET,PAPI_FUL_ICY,NOT_DERIVED,CPU_INSDUAL
PRESET,PAPI_L2_TCM,NOT_DERIVED,CPU_L2MISSALL
PRESET,PAPI_L2_TCA,NOT_DERIVED,CPU_L2REQ
#
CPU,BGQ
#
# Conditional Branching
PRESET,PAPI_BR_CN,NOT_DERIVED,PEVT_INST_XU_BRC
PRESET,PAPI_BR_INS,NOT_DERIVED,PEVT_XU_BR_COMMIT
PRESET,PAPI_BR_MSP,NOT_DERIVED,PEVT_XU_BR_MISPRED_COMMIT
PRESET,PAPI_BR_NTK,DERIVED_POSTFIX,N0|N1|-|N2|-|,PEVT_INST_XU_BRC,PEVT_XU_BR_TAKEN_COMMIT,PEVT_INST_XU_BRU
#PRESET,PAPI_BR_NTK,DERIVED_SUB,PEVT_INST_XU_BRC,PEVT_XU_BR_TAKEN_COMMIT # Not sure if branches_taken includes unconditional branches as well
PRESET,PAPI_BR_PRC,DERIVED_SUB,PEVT_INST_XU_BRC,PEVT_XU_BR_MISPRED_COMMIT
PRESET,PAPI_BR_TKN,DERIVED_SUB,PEVT_XU_BR_TAKEN_COMMIT,PEVT_INST_XU_BRU
#PRESET,PAPI_BR_TKN,NOT_DERIVED,PEVT_XU_BR_TAKEN_COMMIT # Not sure if branches_taken includes unconditional branches as well
PRESET,PAPI_BR_UCN,NOT_DERIVED,PEVT_INST_XU_BRU
PRESET,PAPI_BTAC_M,NOT_DERIVED,PEVT_XU_BR_TARG_ADDR_MISPRED_COMMIT
#
# Cache Requests
# none so far
#
# Conditional Store
PRESET,PAPI_CSR_FAL,NOT_DERIVED,PEVT_XU_STCX_FAIL
PRESET,PAPI_CSR_SUC,DERIVED_SUB,PEVT_LSU_COMMIT_STCX,PEVT_XU_STCX_FAIL
PRESET,PAPI_CSR_TOT,NOT_DERIVED,PEVT_LSU_COMMIT_STCX
#
# Floating Point Operations
PRESET,PAPI_FAD_INS,DERIVED_ADD,PEVT_INST_QFPU_FADD,PEVT_INST_QFPU_QADD
PRESET,PAPI_FDV_INS,NOT_DERIVED,PEVT_INST_QFPU_FDIV
PRESET,PAPI_FMA_INS,DERIVED_ADD,PEVT_INST_QFPU_FMA,PEVT_INST_QFPU_QMA
PRESET,PAPI_FML_INS,DERIVED_ADD,PEVT_INST_QFPU_FMUL,PEVT_INST_QFPU_QMUL
PRESET,PAPI_FP_INS,NOT_DERIVED,PEVT_INST_QFPU_ALL
# TODO: for PAPI_FP_OPS it's either FPGRP1 or FPGRP2. Needs to be tested
PRESET,PAPI_FP_OPS,NOT_DERIVED,PEVT_INST_QFPU_FPGRP1
# PRESET,PAPI_FP_OPS,NOT_DERIVED,PEVT_INST_QFPU_FPGRP2
PRESET,PAPI_FP_STAL,NOT_DERIVED,PEVT_IU_AXU_FXU_DEP_HIT_CYC
PRESET,PAPI_FSQ_INS,NOT_DERIVED,PEVT_INST_QFPU_FSQ
#
# Instruction Counting
#PRESET,PAPI_FUL_ICY,NOT_DERIVED,PEVT_IU_TWO_INSTR_ISSUE
PRESET,PAPI_FXU_IDL,NOT_DERIVED,PEVT_AXU_IDLE
PRESET,PAPI_HW_INT,NOT_DERIVED,PEVT_XU_INTS_TAKEN
PRESET,PAPI_INT_INS,NOT_DERIVED,PEVT_INST_XU_GRP_MASK:837800,NOTE,'UPC_P_XU_OGRP_IADD|UPC_P_XU_OGRP_IMUL|UPC_P_XU_OGRP_IDIV|UPC_P_XU_OGRP_ICMP|UPC_P_XU_OGRP_IMOV|UPC_P_XU_OGRP_ILOG|UPC_P_XU_OGRP_BITS'
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PEVT_CYCLES
PRESET,PAPI_TOT_IIS,NOT_DERIVED,PEVT_IU_TOT_ISSUE_COUNT
PRESET,PAPI_TOT_INS,NOT_DERIVED,PEVT_INST_ALL
PRESET,PAPI_VEC_INS,DERIVED_ADD,PEVT_INST_QFPU_GRP_MASK:3FE,PEVT_INST_XU_GRP_MASK:3000000,NOTE,'UPC_P_AXU_OGRP_QADD|UPC_P_AXU_OGRP_QCMP|UPC_P_AXU_OGRP_QCVT|UPC_P_AXU_OGRP_QMA|UPC_P_AXU_OGRP_QMOV|UPC_P_AXU_OGRP_QMUL|UPC_P_AXU_OGRP_QOTH|UPC_P_AXU_OGRP_QRES|UPC_P_AXU_OGRP_QRND + UPC_P_XU_OGRP_QLD|UPC_P_XU_OGRP_QST'
#
# Cache Access
PRESET,PAPI_L1_DCM,DERIVED_ADD,PEVT_LSU_COMMIT_LD_MISSES,PEVT_LSU_COMMIT_ST_MISSES
PRESET,PAPI_L1_DCR,NOT_DERIVED,PEVT_LSU_COMMIT_CACHEABLE_LDS
PRESET,PAPI_L1_DCW,NOT_DERIVED,PEVT_LSU_COMMIT_STS
PRESET,PAPI_L1_ICM,NOT_DERIVED,PEVT_IU_IL1_MISS
PRESET,PAPI_L1_ICR,NOT_DERIVED,PEVT_IU_ICACHE_FETCH
PRESET,PAPI_L1_LDM,DERIVED_ADD,PEVT_IU_IL1_MISS,PEVT_LSU_COMMIT_LD_MISSES
PRESET,PAPI_L1_STM,NOT_DERIVED,PEVT_LSU_COMMIT_ST_MISSES
#PRESET,PAPI_L2_TCH,NOT_DERIVED,PEVT_L2_HITS
#PRESET,PAPI_L2_TCM,NOT_DERIVED,PEVT_L2_MISSES
#
# Data Access
PRESET,PAPI_LD_INS,DERIVED_ADD,PEVT_LSU_COMMIT_CACHEABLE_LDS,PEVT_LSU_COMMIT_CACHE_INHIB_LD_MISSES
# may not be possible
#PRESET,PAPI_LST_INS,DERIVED_POSTFIX,N0|N1|+|N2|+|,PEVT_LSU_COMMIT_CACHEABLE_LDS,PEVT_LSU_COMMIT_CACHE_INHIB_LD_MISSES,PEVT_LSU_COMMIT_STS
#PRESET,PAPI_MEM_RCY,NOT_DERIVED,PEVT_IU_RAW_DEP_HIT_CYC
#PRESET,PAPI_PRF_DM,NOT_DERIVED,PEVT_LSU_COMMIT_DCBT_MISSES
PRESET,PAPI_RES_STL,NOT_DERIVED,PEVT_IU_IS1_STALL_CYC
PRESET,PAPI_SR_INS,NOT_DERIVED,PEVT_LSU_COMMIT_STS
PRESET,PAPI_STL_CCY,DERIVED_SUB,PEVT_CYCLES,PEVT_INST_ALL
PRESET,PAPI_STL_ICY,DERIVED_SUB,PEVT_CYCLES,PEVT_IU_TOT_ISSUE_COUNT
PRESET,PAPI_SYC_INS,NOT_DERIVED,PEVT_INST_XU_SYNC
#
# TLB Operations
PRESET,PAPI_TLB_DM,DERIVED_ADD,PEVT_MMU_TLB_MISS_DIRECT_DERAT,PEVT_MMU_TLB_MISS_INDIR_DERAT
PRESET,PAPI_TLB_IM,NOT_DERIVED,PEVT_MMU_TLB_MISS_DIRECT_DERAT
PRESET,PAPI_TLB_SD,NOT_DERIVED,PEVT_MMU_TLBIVAX_SNOOP_TOT
PRESET,PAPI_TLB_TL,DERIVED_POSTFIX,N0|N1|+|N2|+|,PEVT_MMU_TLB_MISS_DIRECT_DERAT,PEVT_MMU_TLB_MISS_INDIR_DERAT,PEVT_MMU_TLB_MISS_DIRECT_IERAT

#################################
# Intel MIC / Xeon-Phi / Knights Corner
CPU,knc
#
PRESET,PAPI_BR_INS,NOT_DERIVED,BRANCHES:mg=1:mh=1
PRESET,PAPI_BR_MSP,NOT_DERIVED,BRANCHES_MISPREDICTED:mg=1:mh=1
PRESET,PAPI_L1_ICM,NOT_DERIVED,CODE_CACHE_MISS:mg=1:mh=1
PRESET,PAPI_TLB_IM,NOT_DERIVED,CODE_PAGE_WALK:mg=1:mh=1
PRESET,PAPI_L1_ICA,NOT_DERIVED,CODE_READ:mg=1:mh=1
PRESET,PAPI_TOT_CYC,NOT_DERIVED,CPU_CLK_UNHALTED:mg=1:mh=1
PRESET,PAPI_TLB_DM,NOT_DERIVED,DATA_PAGE_WALK:mg=1:mh=1
PRESET,PAPI_LD_INS,NOT_DERIVED,DATA_READ:mg=1:mh=1
PRESET,PAPI_SR_INS,NOT_DERIVED,DATA_WRITE:mg=1:mh=1
PRESET,PAPI_L1_DCM,NOT_DERIVED,DATA_READ_MISS_OR_WRITE_MISS:mg=1:mh=1
PRESET,PAPI_L1_DCA,NOT_DERIVED,DATA_READ_OR_WRITE:mg=1:mh=1
PRESET,PAPI_TOT_INS,NOT_DERIVED,INSTRUCTIONS_EXECUTED:mg=1:mh=1
PRESET,PAPI_L2_LDM,NOT_DERIVED,L2_READ_MISS:mg=1:mh=1
PRESET,PAPI_VEC_INS,NOT_DERIVED,VPU_INSTRUCTIONS_EXECUTED:mg=1:mh=1

CPU,BGP
# The following PAPI presets are accurate for all application nodes
# using SMP processing for zero or one threads.  The appropriate native
# hardware counters mapped to the following PAPI preset counters are
# only collected for processors 0 and 1 for each physical compute card.
# The values are correct for other processing mode/thread combinations,
# but only for those application nodes running on processor 0 or 1 of
# a given physical compute card.
PRESET,PAPI_L1_DCM,DERIVED_ADD,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS
PRESET,PAPI_L1_ICM,DERIVED_ADD,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_L1_TCM,DERIVED_ADD,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_CA_SNP,DERIVED_ADD,PNE_BGP_PU0_L1_INVALIDATION_REQUESTS,PNE_BGP_PU1_L1_INVALIDATION_REQUESTS
PRESET,PAPI_PRF_DM,DERIVED_ADD,NE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_FMA_INS,DERIVED_ADD,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4
PRESET,PAPI_FP_INS,DERIVED_ADD,PNE_BGP_PU0_FPU_ADD_SUB_1,PNE_BGP_PU1_FPU_ADD_SUB_1,PNE_BGP_PU0_FPU_MULT_1,PNE_BGP_PU1_FPU_MULT_1,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_DIV_1,PNE_BGP_PU1_FPU_DIV_1,PNE_BGP_PU0_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU0_FPU_ADD_SUB_2,PNE_BGP_PU1_FPU_ADD_SUB_2,PNE_BGP_PU0_FPU_MULT_2,PNE_BGP_PU1_FPU_MULT_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4,PNE_BGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS
PRESET,PAPI_LD_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS
PRESET,PAPI_SR_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_STORES,PNE_BGP_PU1_DATA_STORES
PRESET,PAPI_LST_INS,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS,PNE_BGP_PU0_DATA_STORES,PNE_BGP_PU1_DATA_STORES
PRESET,PAPI_L1_DCH,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT
PRESET,PAPI_L1_DCA,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS
PRESET,PAPI_L1_DCR,DERIVED_ADD,PNE_BGP_PU0_DATA_LOADS,PNE_BGP_PU1_DATA_LOADS
PRESET,PAPI_L1_ICH,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT
PRESET,PAPI_L1_ICA,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_L1_ICR,DERIVED_ADD,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_L1_ICW,DERIVED_ADD,PNE_BGP_PU0_ICACHE_LINEFILLINPROG,PNE_BGP_PU1_ICACHE_LINEFILLINPROG
PRESET,PAPI_L1_TCH, DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,
PRESET,PAPI_L1_TCA,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS,PNE_BGP_PU0_DCACHE_LINEFILLINPROG,PNE_BGP_PU1_DCACHE_LINEFILLINPROG
PRESET,PAPI_L1_TCR,DERIVED_ADD,PNE_BGP_PU0_DCACHE_HIT,PNE_BGP_PU1_DCACHE_HIT,PNE_BGP_PU0_ICACHE_HIT,PNE_BGP_PU1_ICACHE_HIT,PNE_BGP_PU0_DCACHE_MISS,PNE_BGP_PU1_DCACHE_MISS,PNE_BGP_PU0_ICACHE_MISS,PNE_BGP_PU1_ICACHE_MISS
PRESET,PAPI_L1_TCW,DERIVED_ADD,PNE_BGP_PU0_DCACHE_LINEFILLINPROG,PNE_BGP_PU1_DCACHE_LINEFILLINPROG,PNE_BGP_PU0_ICACHE_LINEFILLINPROG,PNE_BGP_PU1_ICACHE_LINEFILLINPROG
PRESET,PAPI_FP_OPS,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|N4|2|*|+|N5|2|*|+|N6|13|*|+|N7|13|*|+|N8|+|N9|+|N10|2|*|+|N11|2|*|+|N12|2|*|+|N13|2|*|+|N14|4|*|+|N15|4|*|+|N16|2|*|+|N17|2|*|+|,PNE_BGP_PU0_FPU_ADD_SUB_1,PNE_BGP_PU1_FPU_ADD_SUB_1,PNE_BGP_PU0_FPU_MULT_1,PNE_BGP_PU1_FPU_MULT_1,PNE_BGP_PU0_FPU_FMA_2,PNE_BGP_PU1_FPU_FMA_2,PNE_BGP_PU0_FPU_DIV_1,PNE_BGP_PU1_FPU_DIV_1,PNE_BGP_PU0_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_OTHER_NON_STORAGE_OPS,PNE_BGP_PU0_FPU_ADD_SUB_2,PNE_BGP_PU1_FPU_ADD_SUB_2,PNE_BGP_PU0_FPU_MULT_2,PNE_BGP_PU1_FPU_MULT_2,PNE_BGP_PU0_FPU_FMA_4,PNE_BGP_PU1_FPU_FMA_4,PNE_BGP_PU0_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS,PNE_BGP_PU1_FPU_DUAL_PIPE_OTHER_NON_STORAGE_OPS
# The following PAPI presets are accurate for any processing mode of 
# SMP, DUAL, or VN for all application nodes.  The appropriate native 
# hardware counters used for the following PAPI preset counters are
# collected for all four processors for each physical compute card.
PRESET,PAPI_L2_DCM,DERIVED_POSTFIX,N0|N1|+|N2|+|N3|+|N4|-|N5|-|N6|-|N7|-|,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU0_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU1_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU2_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU3_L2_PREFETCH_HITS_IN_STREAM
PRESET,PAPI_L3_LDM,DERIVED_ADD,PNE_BGP_L3_M0_RD0_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD0_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD0_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD0_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD1_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_RD1_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD1_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_RD1_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_R2_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M0_R2_DIR1_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_R2_DIR0_MISS_OR_LOCKDOWN,PNE_BGP_L3_M1_R2_DIR1_MISS_OR_LOCKDOWN
# NOTE:  This value is for the time the counters are active,
# and not for the total cycles for the job.
PRESET,PAPI_TOT_CYC,NOT_DERIVED,PNE_BGP_MISC_ELAPSED_TIME
PRESET,PAPI_L2_DCH,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU1_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU2_L2_PREFETCH_HITS_IN_STREAM,PNE_BGP_PU3_L2_PREFETCH_HITS_IN_STREAM
PRESET,PAPI_L2_DCA,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU0_L2_MEMORY_WRITES,PNE_BGP_PU1_L2_MEMORY_WRITES,PNE_BGP_PU2_L2_MEMORY_WRITES,PNE_BGP_PU3_L2_MEMORY_WRITES
PRESET,PAPI_L2_DCR,DERIVED_ADD,PNE_BGP_PU0_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU1_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU2_L2_PREFETCHABLE_REQUESTS,PNE_BGP_PU3_L2_PREFETCHABLE_REQUESTS
PRESET,PAPI_L2_DCW,DERIVED_ADD,PNE_BGP_PU0_L2_MEMORY_WRITES,PNE_BGP_PU1_L2_MEMORY_WRITES,PNE_BGP_PU2_L2_MEMORY_WRITES,PNE_BGP_PU3_L2_MEMORY_WRITES
PRESET,PAPI_L3_TCA,DERIVED_ADD,PNE_BGP_L3_M0_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M0_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M0_R2_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M1_R2_BURST_DELIVERED_L2,BGP_L3_M0_W0_DEPOSIT_REQUESTS,BGP_L3_M0_W1_DEPOSIT_REQUESTS,BGP_L3_M1_W0_DEPOSIT_REQUESTS,BGP_L3_M1_W1_DEPOSIT_REQUESTS
PRESET,PAPI_L3_TCR,DERIVED_ADD,PNE_BGP_L3_M0_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD0_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_RD1_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M1_R2_SINGLE_LINE_DELIVERED_L2,PNE_BGP_L3_M0_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M0_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M0_R2_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD0_BURST_DELIVERED_L2,PNE_BGP_L3_M1_RD1_BURST_DELIVERED_L2,PNE_BGP_L3_M1_R2_BURST_DELIVERED_L2
PRESET,PAPI_L3_TCW,DERIVED_ADD,PNE_BGP_L3_M0_W0_DEPOSIT_REQUESTS,PNE_BGP_L3_M0_W1_DEPOSIT_REQUESTS,PNE_BGP_L3_M1_W0_DEPOSIT_REQUESTS,PNE_BGP_L3_M1_W1_DEPOSIT_REQUESTS