x86/microcode: Add Zhaoxin cpu microcode update driver

zhaoxin inclusion
category: feature

--------------------

Add support for Zhaoxin CPU in the x86 microcode loading facility
to enable microcode loading during the OS stage. Currently, Zhaoxin
CPU only support early microcode loading.

Signed-off-by: leoliu-oc <[email protected]>

Author: leoliu-oc

arch/x86/Kconfig

@@ -1318,7 +1318,7 @@ config X86_REBOOTFIXUPS
 
 config MICROCODE
 	def_bool y
-	depends on CPU_SUP_AMD || CPU_SUP_INTEL || CPU_SUP_HYGON
+	depends on CPU_SUP_AMD || CPU_SUP_INTEL || CPU_SUP_HYGON || CPU_SUP_ZHAOXIN || CPU_SUP_CENTAUR
 	select CRYPTO_LIB_SHA256 if CPU_SUP_AMD
 
 config MICROCODE_INITRD32

arch/x86/kernel/cpu/microcode/Makefile

@@ -3,3 +3,6 @@ microcode-y				:= core.o
 obj-$(CONFIG_MICROCODE)			+= microcode.o
 microcode-$(CONFIG_CPU_SUP_INTEL)	+= intel.o
 microcode-$(CONFIG_CPU_SUP_AMD)		+= amd.o
+ifneq ($(CONFIG_CPU_SUP_ZHAOXIN)$(CONFIG_CPU_SUP_CENTAUR),)
+microcode-y				+= zhaoxin.o
+endif

arch/x86/kernel/cpu/microcode/core.c

@@ -135,14 +135,15 @@ static bool __init check_loader_disabled_bsp(void)
 void __init load_ucode_bsp(void)
 {
 	unsigned int cpuid_1_eax;
-	bool intel = true;
+	unsigned int x86_vendor;
 
 	if (!have_cpuid_p())
 		return;
 
 	cpuid_1_eax = native_cpuid_eax(1);
+	x86_vendor = x86_cpuid_vendor();
 
-	switch (x86_cpuid_vendor()) {
+	switch (x86_vendor) {
 	case X86_VENDOR_INTEL:
 		if (x86_family(cpuid_1_eax) < 6)
 			return;
@@ -151,11 +152,15 @@ void __init load_ucode_bsp(void)
 	case X86_VENDOR_AMD:
 		if (x86_family(cpuid_1_eax) < 0x10)
 			return;
-		intel = false;
 		break;
 
 	case X86_VENDOR_HYGON:
-		intel = false;
+		break;
+
+	case X86_VENDOR_ZHAOXIN:
+	case X86_VENDOR_CENTAUR:
+		if ((cpuid_eax(0xC0000000) < 0xC0000004) || !(cpuid_edx(0xC0000004) & 0x1))
+			return;
 		break;
 
 	default:
@@ -165,10 +170,21 @@ void __init load_ucode_bsp(void)
 	if (check_loader_disabled_bsp())
 		return;
 
-	if (intel)
+	switch (x86_vendor) {
+	case X86_VENDOR_INTEL:
 		load_ucode_intel_bsp(&early_data);
-	else
+		break;
+	case X86_VENDOR_AMD:
+	case X86_VENDOR_HYGON:
 		load_ucode_amd_bsp(&early_data, cpuid_1_eax);
+		break;
+	case X86_VENDOR_ZHAOXIN:
+	case X86_VENDOR_CENTAUR:
+		load_ucode_zhaoxin_bsp(&early_data);
+		break;
+	default:
+		return;
+	}
 }
 
 void load_ucode_ap(void)
@@ -192,6 +208,11 @@ void load_ucode_ap(void)
 	case X86_VENDOR_HYGON:
 		load_ucode_amd_ap(cpuid_1_eax);
 		break;
+	case X86_VENDOR_ZHAOXIN:
+	case X86_VENDOR_CENTAUR:
+		if ((cpuid_eax(0xC0000000) >= 0xC0000004) && (cpuid_edx(0xC0000004) & 0x1))
+			load_ucode_zhaoxin_ap();
+		break;
 	default:
 		break;
 	}
@@ -254,6 +275,10 @@ static void reload_early_microcode(unsigned int cpu)
 	case X86_VENDOR_HYGON:
 		reload_ucode_amd(cpu);
 		break;
+	case X86_VENDOR_ZHAOXIN:
+	case X86_VENDOR_CENTAUR:
+		reload_ucode_zhaoxin();
+		break;
 	default:
 		break;
 	}
@@ -843,6 +868,9 @@ static int __init microcode_init(void)
 		microcode_ops = init_amd_microcode();
 	else if (c->x86_vendor == X86_VENDOR_HYGON)
 		microcode_ops = init_hygon_microcode();
+	else if (c->x86_vendor == X86_VENDOR_ZHAOXIN ||
+		 c->x86_vendor == X86_VENDOR_CENTAUR)
+		microcode_ops = init_zhaoxin_microcode();
 	else
 		pr_err("no support for this CPU vendor\n");
 

arch/x86/kernel/cpu/microcode/internal.h

@@ -58,6 +58,12 @@ struct cpio_data find_microcode_in_initrd(const char *path);
 #define CPUID_HYGON1 QCHAR('H', 'y', 'g', 'o')
 #define CPUID_HYGON2 QCHAR('n', 'G', 'e', 'n')
 #define CPUID_HYGON3 QCHAR('u', 'i', 'n', 'e')
+#define CPUID_ZHAOXIN1 QCHAR(' ', ' ', 'S', 'h')
+#define CPUID_ZHAOXIN2 QCHAR('a', 'n', 'g', 'h')
+#define CPUID_ZHAOXIN3 QCHAR('a', 'i', ' ', ' ')
+#define CPUID_CENTAUR1 QCHAR('C', 'e', 'n', 't')
+#define CPUID_CENTAUR2 QCHAR('a', 'u', 'r', 'H')
+#define CPUID_CENTAUR3 QCHAR('a', 'u', 'l', 's')
 
 #define CPUID_IS(a, b, c, ebx, ecx, edx)	\
 		(!(((ebx) ^ (a)) | ((edx) ^ (b)) | ((ecx) ^ (c))))
@@ -87,6 +93,12 @@ static inline int x86_cpuid_vendor(void)
 	if (CPUID_IS(CPUID_HYGON1, CPUID_HYGON2, CPUID_HYGON3, ebx, ecx, edx))
 		return X86_VENDOR_HYGON;
 
+	if (CPUID_IS(CPUID_ZHAOXIN1, CPUID_ZHAOXIN2, CPUID_ZHAOXIN3, ebx, ecx, edx))
+		return X86_VENDOR_ZHAOXIN;
+
+	if (CPUID_IS(CPUID_CENTAUR1, CPUID_CENTAUR2, CPUID_CENTAUR3, ebx, ecx, edx))
+		return X86_VENDOR_CENTAUR;
+
 	return X86_VENDOR_UNKNOWN;
 }
 
@@ -137,4 +149,19 @@ static inline void reload_ucode_intel(void) { }
 static inline struct microcode_ops *init_intel_microcode(void) { return NULL; }
 #endif  /* !CONFIG_CPU_SUP_INTEL */
 
+#if defined(CONFIG_CPU_SUP_ZHAOXIN) || defined(CONFIG_CPU_SUP_CENTAUR)
+void load_ucode_zhaoxin_bsp(struct early_load_data *ed);
+void load_ucode_zhaoxin_ap(void);
+void reload_ucode_zhaoxin(void);
+struct microcode_ops *init_zhaoxin_microcode(void);
+#else /* CONFIG_CPU_SUP_ZHAOXIN || CONFIG_CPU_SUP_CENTAUR */
+static inline void load_ucode_zhaoxin_bsp(struct early_load_data *ed) { }
+static inline void load_ucode_zhaoxin_ap(void) { }
+static inline void reload_ucode_zhaoxin(void) { }
+static inline struct microcode_ops *init_zhaoxin_microcode(void)
+{
+	return NULL;
+}
+#endif  /* !CONFIG_CPU_SUP_ZHAOXIN && !CONFIG_CPU_SUP_CENTAUR */
+
 #endif /* _X86_MICROCODE_INTERNAL_H */