Skip to content

Commit 802c2ad

Browse files
committed
correct the annotation at the end of file dftd3.h
1 parent b1adbf3 commit 802c2ad

File tree

1 file changed

+10
-11
lines changed
  • source/module_hamilt_general/module_vdw

1 file changed

+10
-11
lines changed

source/module_hamilt_general/module_vdw/dftd3.h

Lines changed: 10 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -410,22 +410,21 @@ def complete(vdw_method, value):
410410
'op': {'s9': 1.0, 'alp': 14.0}
411411
}
412412
ALL_KEYS = {'s6', 'rs6', 'a1', 's8', 'rs8', 'a2', 's9', 'alp', 'bet'}
413+
EQUIVALENT = {'rs6': 'a1', 'a1': 'rs6', 'rs8': 'a2', 'a2': 'rs8'}
413414
out = value.copy()
415+
for k in ALL_KEYS:
416+
equilk = EQUIVALENT.get(k, k)
417+
val = [out.get(k), out.get(equilk),
418+
DEFAULT[vdw_method].get(k), DEFAULT[vdw_method].get(equilk)]
419+
val = [v for v in val if v is not None]
420+
val = [0.0] if not val else val
421+
out[k] = val[0]
422+
out[equilk] = out[k]
414423
# equivalent?
415424
# according to
416425
# abacus-develop/source/module_hamilt_general/module_vdw/vdwd3_parameters.cpp
417426
# https://abacus.deepmodeling.com/en/latest/advanced/input_files/input-main.html
418-
if 'rs6' in out:
419-
out['a1'] = out['rs6']
420-
if 'a1' in out:
421-
out['rs6'] = out['a1']
422-
if 'rs8' in out:
423-
out['a2'] = out['rs8']
424-
if 'a2' in out:
425-
out['rs8'] = out['a2']
426-
for k in ALL_KEYS:
427-
if k not in out:
428-
out[k] = DEFAULT[vdw_method].get(k, 0.0)
427+
429428
return out
430429
431430
def make_stdmap(data):

0 commit comments

Comments
 (0)