LLM Circuit Analysis

[shanemmattner]

I opened up #239 but I'm posting here for visibility.

I've been using LLM's to check my circuit theory and help with circuit design and PCB design in general. I thought SKiDL's python based circuit descriptions would work great with LLM's. So far the results seem to be promising, but it's clear that I need to include more information on each subcircuit, part, and connections for the LLM to give better analysis.

Here's an example output analysis file:
subcircuits_analysis.txt
Which was generated from running this code:

from skidl import *
import os

@subcircuit
def rc_filter(inp, outp, gnd):
    """RC low-pass filter"""
    r = Part("Device", 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', value='10K')
    c = Part("Device", 'C', footprint='Capacitor_SMD:C_0805_2012Metric', value='0.1uF')
    inp += r[1]
    r[2] += c[1]
    c[2] += gnd
    outp += r[2]

@subcircuit
def input_protection(inp, outp, gnd):
    """Input protection and bulk capacitance"""
    d_protect = Part("Device", 'D',
                    footprint='Diode_SMD:D_SOD-123',
                    value='1N4148W')
    c_bulk = Part("Device", 'C',
                  footprint='Capacitor_THT:CP_Radial_D10.0mm_P5.00mm',
                  value='100uF')
    
    inp += d_protect['A']
    outp += d_protect['K']
    inp += c_bulk[1]
    gnd += c_bulk[2]

@subcircuit
def voltage_regulator(inp, outp, gnd):
    """5V voltage regulator with decoupling caps"""
    reg = Part("Regulator_Linear", "LM7805_TO220",
               footprint="Package_TO_SOT_THT:TO-220-3_Vertical")
    cin = Part("Device", 'C', footprint='Capacitor_SMD:C_0805_2012Metric', value='10uF')
    cout = Part("Device", 'C', footprint='Capacitor_SMD:C_0805_2012Metric', value='10uF')
    inp += cin[1], reg['VI']
    cin[2] += gnd
    reg['GND'] += gnd
    reg['VO'] += cout[1], outp
    cout[2] += gnd

@subcircuit
def voltage_divider(inp, outp, gnd):
    """Basic voltage divider subcircuit"""
    r1 = Part("Device", 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', value='1K')
    r2 = Part("Device", 'R', footprint='Resistor_SMD.pretty:R_0805_2012Metric', value='500')
    inp += r1[1]
    r1[2] += r2[1]
    r2[2] += gnd
    outp += r1[2]

@subcircuit
def output_termination(inp, gnd):
    """Output termination resistor"""
    r_term = Part("Device", 'R',
                  footprint='Resistor_SMD.pretty:R_0805_2012Metric',
                  value='100K')
    inp += r_term[1]
    gnd += r_term[2]

@subcircuit
def power_section(raw_in, reg_out, filt_out, gnd):
    """Power section with regulation and filtering"""
    protected_in = Net()
    input_protection(raw_in, protected_in, gnd)
    voltage_regulator(protected_in, reg_out, gnd)
    rc_filter(reg_out, filt_out, gnd)

@subcircuit
def double_divider(inp, outp, gnd):
    """Two voltage dividers in series with termination"""
    mid = Net()
    voltage_divider(inp, mid, gnd)
    voltage_divider(mid, outp, gnd)
    output_termination(outp, gnd)

@subcircuit
def complete_circuit():
    """Top level circuit connecting all subcircuits"""
    vin = Net()
    vreg = Net()
    vfilt = Net()
    vout = Net()
    gnd = Net()

    power_section(vin, vreg, vfilt, gnd)
    double_divider(vfilt, vout, gnd)

# Create the complete circuit
complete_circuit()

# Analyze each subcircuit separately using the new function
results = default_circuit.analyze_subcircuits_with_llm(
    api_key=os.getenv("ANTHROPIC_API_KEY"),
    output_file="subcircuits_analysis.txt"
)

# Print analysis results
if results["success"]:
    print("\nAnalysis Results:")
    for hier, analysis in results["subcircuits"].items():
        print(f"\nSubcircuit: {hier}")
        if analysis["success"]:
            print(f"Analysis completed in {analysis['request_time_seconds']:.2f} seconds")
            print(f"Tokens used: {analysis['prompt_tokens'] + analysis['response_tokens']}")
        else:
            print(f"Analysis failed: {analysis['error']}")
            
    print(f"\nTotal analysis time: {results['total_time_seconds']:.2f} seconds")
    print(f"Total tokens used: {results['total_tokens']}")
else:
    print(f"\nOverall analysis failed: {results.get('error', 'Unknown error')}")

[tapegoji]

Shane,
I love your idea. and In fact I have been thinking (and partially working) on a similar thing with SKiDL. Let's

I sent you a LinkedIn request.

[JustTryingToGetSomeWorkDone]

Hello! I've recently been working a little on getting ChatGPT o4 to output circuit schematics in SKiDL. I have been working with electronics and PCBs for a while and then started doing it for work. My hobby is building modular synthesizers, and I've been asking ChatGPT for completely original ideas or variations of modules using new math and concepts. It's quite fun even just to read. ChatGPT typically offers to share a schematic with me and occasionally I accept. The results have always been, and still are, quite terrible. A low detail block diagram with a couple of lines maybe pointing in the right directions.... Until yesterday when I saw it attempting to use SKiDL. It didn't have the library installed in its built in interpreter, but I installed it locally and fell into the rabbit hole.

I noticed that we can use KiCAD projects and convert them to SKiDL. That gives us a great path forward in training any AI, or LLM in particular, to be able to build functioning circuits. I'm rather sad that KiCAD removed the ability to import net lists into the schematic editor, so we'll have to either try to get that functionality in SKiDL updated (generate_schematic), or just go straight to board layouts. Either is ok, I suppose, since the SKiDL file IS a schematic already.. just one that isn't as easy to read with human eyes.

I've found that ChatGPT needs a lot of hand holding and pushing from behind to build a functioning circuit. In its first attempt, it placed a couple of ICs and half a dozen resistors, but nothing else. Power seemed to be correctly hooked up, but an opamp with no capacitors is not going to work at all.

I'll be continuing to experiment, and I'll share my results as things improve.

I'm a self taught programmer, and I can do most things that I need doing (mostly embedded), and I'm alright with reading, editing, some light debugging, but deep object oriented stuff I'm still quite amateurish with. I'll help where I can, but don't be too surprised if I end up in over my head sometimes. I find SKiDL is similar in nature to OpenSCAD, so I think I'll pick it up rather quickly.

[Shaurya-Sethi]

As you exercise netlist_to_skidl, please raise issues for whatever problems/errors you find. That utility doesn't get a lot of attention in the SKiDL unit tests so there may be errors.

Will do! And if possible I'll try to provide fixes for the same as PRs for you to review. Thanks for the heads up.

edit: I just forked the repo and I see that in addition to the development branch that you mentioned, there's also an llm branch - which one should I take a closer look at? Thanks in advance

[devbisme]

Use the development branch; it has the newest netlist_to_skidl. The LLM branch hasn't been touched in a while.

[Shaurya-Sethi]

---

Request for Help: SKiDL Search with KiCad 5 Libraries on Windows 11

Hi @devbisme,

I’m encountering issues using SKiDL to search for parts in the classic KiCad 5 .lib symbol libraries (not the newer KiCad 6+ .sym format). Here are the details:

---

System Information

• OS: Windows 11
• Python Version: 3.12
• SKiDL Installation: Latest version installed via pip

---

Setup

1. I downloaded the official KiCad 5.1.10 symbol library zip from GitLab.

2. I also downloaded the latest KiCad symbol library for comparison.

3. My KICAD_SYMBOL_DIR environment variable is set to the folder containing dozens of .lib files:

   KICAD_SYMBOL_DIR=C:\Users\shaur\Downloads\kicad-symbols-5.1.10
   

4. When I run the following in Python:

   from skidl import search
   print(list(search("LM324")))

   I get no results (the output is [] or a NoneType not iterable error).

5. If I set KICAD6_SYMBOL_DIR, KICAD7_SYMBOL_DIR, etc., to a folder with KiCad 6+ .sym libraries (from kicad-symbols-master), part search works—but it uses the .sym files, which are incompatible with my KiCad 5 workflow. Additionally, this approach is slow.

---

Issue

My project depends on generating netlists and code compatible with KiCad 5’s .lib system so that I can view the generated schematic. However, SKiDL does not seem to recognize the .lib files in KICAD_SYMBOL_DIR.

---

Checks I’ve Done

• The path in KICAD_SYMBOL_DIR contains the expected .lib files (e.g., LM324.lib, Device.lib).
• No higher-version KICAD*_SYMBOL_DIR variables are set during testing with .lib files.
• SKiDL works for part search with .sym files but fails with .lib.

---

Questions

1. Is there a special SKiDL version or installation option required for .lib support on Windows?
2. Is there a known issue or workaround for enabling SKiDL to search .lib libraries in modern Python/Windows setups?
3. Are there additional steps needed to “register” or index .lib libraries for SKiDL’s part search?
4. Are there diagnostic steps I can take to identify why the .lib files are not being detected?

---

Additional Context

• This seems related to Issue #237.
• Would you recommend using the latest KiCad symbol libraries for part lookup and code generation, but opening the schematic files in KiCad 5?

Any advice or guidance would be greatly appreciated. Thank you for your time and for creating SKiDL!

Best regards,
Shaurya

---

[devbisme]

I wrote a reply with a possible solution at #262.

[Shaurya-Sethi]

hi @devbisme
I wanted to ask if all python 3 versions are compatible with kicad5.1 's pcbnew for the internal scripting that skidl does for generating pcbs? Also, since you have mentioned that the schematic generation is only possible with kicad 5, so should I use the same for pcb generation as well? Thanks in advance for your time and help!

[eugenio]

Hello all, recently I came across this library and I decided to investigate the letterature regarding netlist generation by LLMs.
I think I found an interesting article that I link here.
The researchers behind this article used a dataset, that you can download, to fine tune a series of LLMs to the generation of netlists, so I fell into the rabbit hole and in a couple of days with the great help of Claude code I designed a pipeline that downloads a LLM from hugging-face and tunes it to output netlists from textual prompts.
So far the results are largely unsatisfying because my graphic card is not fully supported by the rocm drivers yet, and this makes the model crash on load.
I filed a bug report to AMD about the issue I encountered will see if the things improve once they fix the bug.
If someone here is interested and has an NVIDIA GPU with at least 24 GB of VRAM I can push my pipeline to github for evaluation purpose.

Bests to all,
Eugenio

[Shaurya-Sethi]

@eugenio You might want to try Google Cloud Platform for this. They offer 300USD worth of free credits and you can get a L4 GPU which has 24GB VRAM. I did the same for fine tuning a LLM using unsloth QLoRA. You can find the fine tuning script for reference in my repo: transqlate

[eugenio]

Thanks for the tip @Shaurya-Sethi, I will consider it.

However my problem is not the fine tuning but the token generation...
It's then when the model hangs...

[Shaurya-Sethi]

You could still rent the same GPU I mentioned and do inference on it. You'll need to create a Vertex AI instance configured with the same GPU, and just move your scripts and model weights to the Jupyter lab session that gets created for you. You can then execute there. Hope this helps

[eugenio]

I considered that approach, I even did some research on (cheaper) alternatives to google cloud and AWS. I might do that if the AMD bug doesn't get resolved soon.
Anyway thanks for you advice again!
May I ask you what result did you get with your implementation?

[Shaurya-Sethi]

My implementation of?

[eugenio]

Your implementation of the agentic circuit generation: I believe you call it Circuitron? Il giorno gio 10 lug 2025 alle ore 17:57 Shaurya Sethi < ***@***.***> ha scritto:

…

My implementation of? — Reply to this email directly, view it on GitHub <#241 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AACHMZE32HQCXNPNUSYDVIT3H2ENHAVCNFSM6AAAAABUUH3ENSVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGNZSGI2TMMQ> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[Shaurya-Sethi]

ohh okay. Yeah Its still in development - Having some trouble lately with getting my agents to correctly write SKiDL code but I'll get it working soon and let everyone know here. Hopefully it takes off and the community can make it better as time moves on.

[eugenio]

That's great. If I understood correctly from above, you are lamenting the lack of material on which to train your model, correct? Il giorno gio 10 lug 2025 alle ore 18:05 Shaurya Sethi < ***@***.***> ha scritto:

…

ohh okay. Yeah Its still in development - Having some trouble lately with getting my agents to correctly write SKiDL code but I'll get it working soon and let everyone know here. Hopefully it takes off and the community can make it better as time moves on. — Reply to this email directly, view it on GitHub <#241 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AACHMZHYJKLFDIC2OW5KNEL3H2FMLAVCNFSM6AAAAABUUH3ENSVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGNZSGI3DIOI> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[Shaurya-Sethi]

I'm not taking the fine tuning/training approach at all. I am building an agentic system where specialised agents work sequentially and utilise custom tools and MCP to programmatically generate kicad schematics and pcb layouts using the SKiDL library.

[eugenio]

Ok, thanks for the clarification. I took the liberty of cloning your Circuityron repo and modifying it to work with my local fine-tuned model. I'll let you know how it goes! Thanks again for your help! Il giorno gio 10 lug 2025 alle ore 18:11 Shaurya Sethi < ***@***.***> ha scritto:

…

I'm not taking the fine tuning/training approach at all. I am building an agentic system where specialised agents work sequentially and utilise custom tools and MCP to programmatically generate kicad schematics and pcb layouts using the SKiDL library. — Reply to this email directly, view it on GitHub <#241 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AACHMZGNUEM4MHR3KF436WL3H2GDZAVCNFSM6AAAAABUUH3ENSVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGNZSGI3TEMA> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[Shaurya-Sethi]

I'm not sure if it will work with your current set up since the framework I am using is OpenAI Agents SDK. If you still wish to take a look, the main branch is outdated - view refactor/kg-validation.

[eugenio]

Thanks, I'll check it out! Il giorno gio 10 lug 2025 alle ore 18:32 Shaurya Sethi < ***@***.***> ha scritto:

…

I'm not sure if it will work with your current set up since the framework I am using is OpenAI Agents SDK. If you still wish to take a look, the main branch is outdated - view refactor/kg-validation. — Reply to this email directly, view it on GitHub <#241 (reply in thread)>, or unsubscribe <https://github.com/notifications/unsubscribe-auth/AACHMZDDJHCJUY7LOPUUBQD3H2IS7AVCNFSM6AAAAABUUH3ENSVHI2DSMVQWIX3LMV43URDJONRXK43TNFXW4Q3PNVWWK3TUHMYTGNZSGI4DSMY> . You are receiving this because you were mentioned.Message ID: ***@***.***>

[devbisme]

Wow, there's a lot of stuff in circuitron! I'm going to read through it and see how I can better support things like that in SKiDL. Let me know your suggestions. I'm excited by all these efforts to insert AI!

One thing I'm doing is to use the docstring for a subcircuit as a description of what the subcircuit is intended to do. I'm also going to allow subcircuits, Groups, and Parts to have a purpose attribute in which you can enter text that describes what function is provided by this particular instantiation of components. It might go something like this:

with Group(purpose='VCC power supply decoupling')):
  for _ in range(10):
    c = Part('Device', 'C', value='0.1uF', purpose='Decoupling cap')
    VCC & c & GND # Attach cap between power and ground.

Hopefully, this would help guide an AI-assisted circuit reviewer in understanding the circuit.

With regards to schematics and KiCad V5 versus more modern versions, I would avoid dependence upon generating schematics. As I've said before, my code doesn't output very nice-looking schematics and often fails to generate a correctly-routed schematic at all. My naive notion of AI-assisted circuit designing looks like this:

flowchart LR
  A[AI Circuit Generator] --> B[(SKiDL Code)] --> C[Python] --> D[(netlist)] --> E[PCBNEW]
  B --> F[AI Design Reviewer] --> G[(Review)]

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I think we can pack everything into the netlist file that PCBNEW needs to layout a PCB. There doesn't appear to be a need for a schematic (especially an editable schematic which leads to a whole lot of issues). And this allows the use of KiCad 6, 7, 8, 9, 10, ...

However, schematics can be helpful for feedback and understanding by the designers and downstream consumers of the design. For that reason, generating a static schematic in SVG might be a good idea:

flowchart LR
  A[AI Circuit Generator] --> B[(SKiDL Code)] --> C[Python] --> D[(netlist)] --> E[PCBNEW]
  C -.-> H[(Static SVG Schematic)]
  B --> F[AI Design Reviewer] --> G[(Review)]

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The SVG schematics could be output by the existing schematic generation code, but I'd need to improve that code to fix the existing problems it has. That's not something I'm planning to do soon.

With regards to examples for training the AI, the development branch of SKiDL includes a utility called netlist_to_skidl that will take a KiCad .net file and create SKiDL code that reflects the hierarchy found in the netlist. This SKiDL code could be used directly for training or maybe SKiDL could include a function that allows it to output training data (similar to how it outputs netlists, XML, etc.).

flowchart LR
A[(KiCad netlist file)] --> B[netlist_to_skidl] --> C1[(SKiDL file 1)]
B --> C2[(Skidl File 2)]
B --> C3[(Skidl File 3)]
C1 --> C2
C1 --> C3

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[Shaurya-Sethi]

I'm glad you took the time to check it out! I actually stuck to the stable skidl version for circuitron because the agents in the system depend on referencing the official SKiDL documentation at https://devbisme.github.io/skidl/ which won't be updated until you release the next SKiDL version. Moreover, the validation agents that utilise SKiDL source code (I parsed your repo into a neo4j graph) would then start reporting incorrectly if there were a mismatch in the documentation and the knowledge graph.

My pipeline ensures that netlist, SVG, schematic, and pcb layouts are always generated - just for convenience. There is no dependency on schematic generation. I am still working on this project and hope to finish making a stable version available soon which you can test and let me know about any improvements or additional features that you would like to see.

To think of a few that I will add in the near future are:

1. Utilising the sequential thinking MCP in the plan stages to make planning even better.
2. A memory bank feature (inspired from Cline)+ Project memory (instead of the current single design per session) to enable users to work on large projects with shared context and multiple designs.
3. Support for local models and providers other than OpenAI
4. Improving initial dependency set up by using docker compose and interactive entering of environment variables
5. Perhaps some schematic beautification agent following the documentation - section: "SVG Schematics"

Lastly, I tried the netlist to skidl utility from the main branch, and it does work but the resultant code produced by it isnt well formatted and I don't think its usable in that state. Also, I was unable to find many kicad netlists to even do this conversion so fine tuning is out of question - If anything, I would in the future look towards adding skidl codes corresponding to various designs in the "code examples" in the knowledge base for my agents to refer to while building anything similar - This would be better in my opinion than fine tuning.

[devbisme]

Lastly, I tried the netlist to skidl utility from the main branch, and it does work but the resultant code produced by it isnt well formatted and I don't think its usable in that state.

Yes, the released code outputs a flat description without hierarchy, so it throws away a lot of design information.

Also, I was unable to find many kicad netlists to even do this conversion

You can use the KiCad command line interface to programmatically generate netlists from the schematics in a KiCad project. And you can find a lot of existing KiCad projects here. You can even get the JSON for all the existing KiCad-related repos on Github if you want to try automatically harvesting projects. So that avenue is open if you ever need it.

[eugenio]

I started working on the KiCad-python APIs to add functionality for the addition of components, symbols, and values in Eeschema, the schematic editor of KiCad. I also added the missing classes and methods for the APIs in Kicad's sources, and it compiles correctly.
I am having trouble writing the correct methods for component positioning and finding sheet coordinates in the APIs, to place the components within the sheet's boundaries. In your knowledge, is there some material on how to do it correctly in the KiCad development docs?

[devbisme]

Sorry, but I don't have any detailed knowledge of KiCad development. It sounds like you're working on KiCad's yet-to-be-released EESCHEMA API? You should probably join the KiCad developer's group and ask them these questions.