Introducing Circuitron: An Agentic, Open Source PCB Design Accelerator Built with SKiDL

[Shaurya-Sethi]

Hi everyone,

I’m excited to share a project I’ve been building that heavily leverages SKiDL at its core: Circuitron – an agent-driven, AI-powered PCB design accelerator.

What is Circuitron?

Circuitron is an open source tool designed to transform natural language requirements into working SKiDL scripts, KiCad schematics, and PCB layout files. It integrates a multi-agent workflow (powered by OpenAI Agents SDK and RAG via Model Context Protocol) to plan, reason, select real parts, generate code, validate, and iterate until a clean, production-ready design is created.

Key features:

• Reasoning-driven workflow: Each design is broken down into stepwise plans with full chain-of-thought output, all visible to the user.
• Real part selection: Searches actual KiCad libraries (in Docker) to ensure all chosen components are available and match specs.
• Automatic schematic & PCB generation: Outputs .sch, netlists, SVG previews, and .kicad_pcb files—ready for KiCad.
• Iterative correction loop: Agents validate and correct code, performing ERC until the design is error-free.
• Containerized toolchain: Ensures reproducibility with Dockerized KiCad and Python environments.
• Retrieval-Augmented Generation: Surfaces relevant SKiDL docs and examples at every step for accurate code generation and validation.

Full project overview and workflow details are in the README and overview.

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Why am I posting here?

SKiDL is the backbone of Circuitron’s schematic and PCB generation. The flexibility and power of SKiDL made it possible to automate schematic creation, netlist and PCB file generation, and integrate with agentic workflows. I believe this kind of intelligent, transparent automation could be a big productivity boost—while always keeping engineers in the loop and in control.

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Development Status and Call for Community Involvement

Circuitron is still under active development and very much a work-in-progress. There is tremendous scope for improvement, and I want to be transparent that it’s not perfect—there are likely many issues, edge cases, and missing features that will only come to light through broader usage and feedback. Community contributions, testing, and suggestions are hugely valuable to help address these challenges and shape Circuitron into a truly production-grade, reliable tool.

The goal is to make Circuitron a robust, production-grade, fully open source tool for PCB and schematic design, accessible to the entire electronics community. I’d love for the SKiDL community to:

• Check out the project, try out the workflow, and share feedback or suggestions
• Contribute code, documentation, or ideas—especially relating to advanced SKiDL features, validation, or schematic beautification
• Help ensure compatibility and develop new agentic features that enhance SKiDL-based design

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Links:

• Circuitron GitHub Repo
• SKiDL Documentation (used as RAG source)

If you’re interested or have ideas, please reply here or open issues/PRs on the Circuitron repo. I also have a Discussions page on my Circuitron repo: https://github.com/Shaurya-Sethi/circuitron/discussions — you’re welcome to join the conversation there! Let’s work together to build the next generation of open source PCB design tools.

Thanks to @devbisme and the SKiDL community for this fantastic foundation.

— Shaurya

[devbisme]

Thanks for making this available, @Shaurya-Sethi ! I'm going to try it out within the next few days. I see you have discussions enabled on the Circuitron repo. I hope you get some interesting conversations there. I wish there were a way to cross-post so that some of those conversations would be mirrored here.

[Shaurya-Sethi]

Hi. You might not be in the circuitron directory. Also don't forget to activate the project's virtual environment. Additionally, I made some updates to the repository so please pull the latest changes and then reinstall the package with pip install -e .

[Shaurya-Sethi]

It does work for me - last I checked was a day ago.

[johnthagen]

I spent 1.5 years trying to generate schematics from SKiDL. At that time, KiCad 5 was the current version. By the time I finished, it was KiCad 7 and the schematic file format had changed completely.

I think the best way to solve this problem is for KiCad to add an IPC API for the schematic editor. I've also struggled before to keep up with the binary changes in KiCad file formats, but an API offloads that work to KiCad itself.

KiCad has a new IPC API that is much nicer to use

• https://gitlab.com/kicad/code/kicad-python

Currently it only supports the physical layout (PCB Editor) but a new API for the schematic editor is a highly requested feature

• https://gitlab.com/kicad/code/kicad/-/issues/2077
• https://gitlab.com/kicad/code/kicad-python/-/issues/40

I think using this API when it is created would be more sustainable approach for SKiDL (and others wanting to generate KiCad schematics).

Voting for these issues would help signal to the KiCad team the demand. (And I'm sure they would also accept contributions.)

[devbisme]

APIs are nice, but they can change between versions just like file formats. This happened multiple times with the pcbnew.py library which caused plugins to stop working. I'm not sure if the new IPC API will suffer this same problem or not. It also currently requires a live connection to a running instance of KiCad. And a companion EESCHEMA API has been discussed for years with no tangible results, so I don't place a lot of hope on that becoming a viable path within the next few years. But who knows? I'm willing to be surprised.

[johnthagen]

All totally valid points 👍.

[devbisme]

Ah, pip install...! So simple. Thank you!

[Shaurya-Sethi]

No worries, have a nice day :)

[Shaurya-Sethi]

@devbisme I'm having some trouble with SKiDL's schematic and PCB file generations. The associated functions are being called but the files are either not being generated in the docker container, or I'm unable to copy them out and present them to the user.

Can you help look into this? If this is associated with not having proper footprints selected, then it's understandable. (which I doubt it is; at least for generate_schematic)

The SVG images and netlists are being generated as normal.

[devbisme]

Which version of SKiDL are you using? If it's the newest release, did dropping back to the previous version work OK?

I just tried generating a schematic with SKiDL 2.1.1 and that worked.

[devbisme]

I found an error in the development branch where SKiDL was generating netlists and schematic files with errors in the library fields for parts. This manifested in schematics as part symbols being replaced with boxes because EESCHEMA couldn't find the symbol files. I'm not sure if this is the error you were/are seeing. In any event, this error only affected the development branch of SKiDL and it didn't prevent the creation of the schematic files, they were just incorrect.

I'll give it a try with my version of circuitron and see if I get the same problems.