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Editorial and typesetting fixes for v0.1
Signed-off-by: Grant Likely <[email protected]>
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source/acknowledgements.rst

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@@ -14,5 +14,4 @@ the Open Firmware Working Group which developed bindings for IEEE-1275.
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We would like to acknowledge their contributions.
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We would also like to acknowledge the contribution of the PowerPC and ARM Linux
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communities that developed and implemented the flattened device
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tree concept.
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communities that developed and implemented the flattened devicetree concept.

source/device-bindings.rst

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@@ -4,7 +4,7 @@ Device Bindings
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===============
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This chapter contains requirements, known as bindings, for how specific
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types and classes of devices are represented in the device tree. The
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types and classes of devices are represented in the devicetree. The
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compatible property of a device node describes the specific binding (or
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bindings) to which the node complies.
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General Principles
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~~~~~~~~~~~~~~~~~~
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When creating a new device tree representation for a device, a binding
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When creating a new devicetree representation for a device, a binding
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should be created that fully describes the required properties and value
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of the device. This set of properties shall be sufficiently descriptive
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to provide device drivers with needed attributes of the device.
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2. Use the standard properties (defined in sections
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:ref:`sect-standard-properties` and :ref:`sect-interrupts`) as
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applicable for the new device. This usage typically includes the
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``reg`` and interrupts properties at a minimum.
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``reg`` and ``interrupts`` properties at a minimum.
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3. Use the conventions specified in section :ref:`chapter-device-bindings`
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(Device Bindings) if the new device fits into one the |spec| defined
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number of bytes between registers. The ``reg-shift`` property
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specifies in bytes how far the discrete device registers are
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separated from each other. The individual register location
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is calculated by using following formula: registers address
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is calculated by using following formula: "registers address"
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<< reg-shift. If unspecified, the default value is 0.
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For example, in a system where 16540 UART registers are
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Serial devices compatible to the National Semiconductor 16450/16550 UART
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(Universal Asynchronous Receiver Transmitter) should be represented in
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the device tree using following properties.
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the devicetree using following properties.
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.. tabularcolumns:: l c l J
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.. table:: ns16550 UART Properties
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======================= ===== ===================== ===============================================
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Property Name Usage Value Type Definition
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======================= ===== ===================== ===============================================
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``compatible`` R <string list> Value shall include ns16550.
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``compatible`` R <string list> Value shall include "ns16550".
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``clock-frequency`` R ``<u32>`` Specifies the frequency (in Hz) of the baud
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rate generator’s input clock
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``current-speed`` OR ``<u32>`` Specifies current serial device speed in bits
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~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
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Network devices based on the IEEE 802.3 collections of LAN standards
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(collectively referred to as Ethernet) may be represented in the device
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tree using following properties, in addition to properties specified of
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(collectively referred to as Ethernet) may be represented in the devicetree
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using following properties, in addition to properties specified of
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the network device class.
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The properties listed in this section augment the properties listed in
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specific to the implementation.
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Recommended values are shown in the following table.
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Example ``phy-connection-type = mii;``
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Example ``phy-connection-type = "mii";``
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=========== ==============================================================
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.. tabularcolumns:: | l J |
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Power ISA Open PIC Interrupt Controllers
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----------------------------------------
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This section specifies the requirements for representing open PIC
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compatible interrupt controllers. An open PIC interrupt controller
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implements the open PIC architecture (developed jointly by AMD and
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This section specifies the requirements for representing Open PIC
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compatible interrupt controllers. An Open PIC interrupt controller
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implements the Open PIC architecture (developed jointly by AMD and
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Cyrix) and specified in The Open Programmable Interrupt Controller (PIC)
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Register Interface Specification Revision 1.2 ?.
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Register Interface Specification Revision 1.2 [b18]_.
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Interrupt specifiers in an open PIC interrupt domain are encoded with
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Interrupt specifiers in an Open PIC interrupt domain are encoded with
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two cells. The first cell defines the interrupt number. The second cell
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defines the sense and level information.
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System-on-a-chip processors may have an internal I/O bus that cannot be
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probed for devices. The devices on the bus can be accessed directly
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without additional configuration required. This type of bus is
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represented as a node with a compatible value of simple-bus.
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represented as a node with a compatible value of "simple-bus".
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.. tabularcolumns:: | l c l J |
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.. table:: ``simple-bus`` Compatible Node Properties

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