@@ -4,7 +4,7 @@ Device Bindings
44===============
55
66This chapter contains requirements, known as bindings, for how specific
7- types and classes of devices are represented in the device tree . The
7+ types and classes of devices are represented in the devicetree . The
88compatible property of a device node describes the specific binding (or
99bindings) to which the node complies.
1010
@@ -20,7 +20,7 @@ Binding Guidelines
2020General Principles
2121~~~~~~~~~~~~~~~~~~
2222
23- When creating a new device tree representation for a device, a binding
23+ When creating a new devicetree representation for a device, a binding
2424should be created that fully describes the required properties and value
2525of the device. This set of properties shall be sufficiently descriptive
2626to provide device drivers with needed attributes of the device.
@@ -33,7 +33,7 @@ Some recommended practices include:
33332. Use the standard properties (defined in sections
3434 :ref: `sect-standard-properties ` and :ref: `sect-interrupts `) as
3535 applicable for the new device. This usage typically includes the
36- ``reg `` and interrupts properties at a minimum.
36+ ``reg `` and `` interrupts `` properties at a minimum.
3737
38383. Use the conventions specified in section :ref: `chapter-device-bindings `
3939 (Device Bindings) if the new device fits into one the |spec | defined
@@ -93,7 +93,7 @@ here to facilitate standardization of names and usage.
9393 number of bytes between registers. The ``reg-shift `` property
9494 specifies in bytes how far the discrete device registers are
9595 separated from each other. The individual register location
96- is calculated by using following formula: “ registers address”
96+ is calculated by using following formula: " registers address"
9797 << reg-shift. If unspecified, the default value is 0.
9898
9999 For example, in a system where 16540 UART registers are
@@ -168,15 +168,15 @@ National Semiconductor 16450/16550 Compatible UART Requirements
168168
169169Serial devices compatible to the National Semiconductor 16450/16550 UART
170170(Universal Asynchronous Receiver Transmitter) should be represented in
171- the device tree using following properties.
171+ the devicetree using following properties.
172172
173173.. tabularcolumns :: l c l J
174174.. table :: ns16550 UART Properties
175175
176176 ======================= ===== ===================== ===============================================
177177 Property Name Usage Value Type Definition
178178 ======================= ===== ===================== ===============================================
179- ``compatible `` R <string list> Value shall include “ ns16550” .
179+ ``compatible `` R <string list> Value shall include " ns16550" .
180180 ``clock-frequency `` R ``<u32> `` Specifies the frequency (in Hz) of the baud
181181 rate generator’s input clock
182182 ``current-speed `` OR ``<u32> `` Specifies current serial device speed in bits
@@ -289,8 +289,8 @@ Ethernet specific considerations
289289~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
290290
291291Network devices based on the IEEE 802.3 collections of LAN standards
292- (collectively referred to as Ethernet) may be represented in the device
293- tree using following properties, in addition to properties specified of
292+ (collectively referred to as Ethernet) may be represented in the devicetree
293+ using following properties, in addition to properties specified of
294294the network device class.
295295
296296The properties listed in this section augment the properties listed in
@@ -326,7 +326,7 @@ the network device class.
326326 specific to the implementation.
327327
328328 Recommended values are shown in the following table.
329- Example ``phy-connection-type = “ mii” ; ``
329+ Example ``phy-connection-type = " mii" ; ``
330330 =========== ==============================================================
331331
332332.. tabularcolumns :: | l J |
@@ -372,13 +372,13 @@ the network device class.
372372Power ISA Open PIC Interrupt Controllers
373373----------------------------------------
374374
375- This section specifies the requirements for representing open PIC
376- compatible interrupt controllers. An open PIC interrupt controller
377- implements the open PIC architecture (developed jointly by AMD and
375+ This section specifies the requirements for representing Open PIC
376+ compatible interrupt controllers. An Open PIC interrupt controller
377+ implements the Open PIC architecture (developed jointly by AMD and
378378Cyrix) and specified in The Open Programmable Interrupt Controller (PIC)
379- Register Interface Specification Revision 1.2 ? .
379+ Register Interface Specification Revision 1.2 [ b18 ]_ .
380380
381- Interrupt specifiers in an open PIC interrupt domain are encoded with
381+ Interrupt specifiers in an Open PIC interrupt domain are encoded with
382382two cells. The first cell defines the interrupt number. The second cell
383383defines the sense and level information.
384384
@@ -420,7 +420,7 @@ specifiers:
420420System-on-a-chip processors may have an internal I/O bus that cannot be
421421probed for devices. The devices on the bus can be accessed directly
422422without additional configuration required. This type of bus is
423- represented as a node with a compatible value of “ simple-bus” .
423+ represented as a node with a compatible value of " simple-bus" .
424424
425425.. tabularcolumns :: | l c l J |
426426.. table :: ``simple-bus`` Compatible Node Properties
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