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Enable some more 2024 migration lints (bytecodealliance#9962)
Most don't produce many warnings except for `rust-2024-incompatible-pat` which required removal of a number of `ref` and `ref mut` keywords throughout the workspace.
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18 files changed

+76
-87
lines changed

18 files changed

+76
-87
lines changed

‎Cargo.toml

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -183,6 +183,10 @@ unused-macro-rules = 'warn'
183183
# bit too noisy to enable wholesale but some selective items are ones we want to
184184
# opt-in to.
185185
keyword_idents_2024 = 'warn'
186+
deprecated-safe-2024 = 'warn'
187+
rust-2024-guarded-string-incompatible-syntax = 'warn'
188+
rust-2024-prelude-collisions = 'warn'
189+
rust-2024-incompatible-pat = 'warn'
186190

187191
# Don't warn about unknown cfgs for pulley
188192
[workspace.lints.rust.unexpected_cfgs]

‎cranelift/codegen/src/ir/dfg.rs

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1262,11 +1262,7 @@ impl DataFlowGraph {
12621262
{
12631263
// We update the position of the old last arg.
12641264
let mut last_arg_data = ValueData::from(self.values[last_arg_val]);
1265-
if let ValueData::Param {
1266-
num: ref mut old_num,
1267-
..
1268-
} = &mut last_arg_data
1269-
{
1265+
if let ValueData::Param { num: old_num, .. } = &mut last_arg_data {
12701266
*old_num = num;
12711267
self.values[last_arg_val] = last_arg_data.into();
12721268
} else {
@@ -1295,7 +1291,7 @@ impl DataFlowGraph {
12951291
.unwrap()];
12961292
let mut data = ValueData::from(*packed);
12971293
match &mut data {
1298-
ValueData::Param { ref mut num, .. } => {
1294+
ValueData::Param { num, .. } => {
12991295
*num -= 1;
13001296
*packed = data.into();
13011297
}

‎cranelift/codegen/src/ir/instructions.rs

Lines changed: 2 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -307,9 +307,7 @@ impl InstructionData {
307307
/// `br_table` returns the empty slice.
308308
pub fn branch_destination<'a>(&'a self, jump_tables: &'a ir::JumpTables) -> &'a [BlockCall] {
309309
match self {
310-
Self::Jump {
311-
ref destination, ..
312-
} => std::slice::from_ref(destination),
310+
Self::Jump { destination, .. } => std::slice::from_ref(destination),
313311
Self::Brif { blocks, .. } => blocks.as_slice(),
314312
Self::BranchTable { table, .. } => jump_tables.get(*table).unwrap().all_branches(),
315313
_ => {
@@ -327,10 +325,7 @@ impl InstructionData {
327325
jump_tables: &'a mut ir::JumpTables,
328326
) -> &'a mut [BlockCall] {
329327
match self {
330-
Self::Jump {
331-
ref mut destination,
332-
..
333-
} => std::slice::from_mut(destination),
328+
Self::Jump { destination, .. } => std::slice::from_mut(destination),
334329
Self::Brif { blocks, .. } => blocks.as_mut_slice(),
335330
Self::BranchTable { table, .. } => {
336331
jump_tables.get_mut(*table).unwrap().all_branches_mut()

‎cranelift/codegen/src/ir/pcc.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -965,15 +965,15 @@ impl<'a> FactContext<'a> {
965965
},
966966
Fact::DynamicRange {
967967
bit_width: bw_dynamic,
968-
min: ref min_dynamic,
969-
max: ref max_dynamic,
968+
min: min_dynamic,
969+
max: max_dynamic,
970970
},
971971
)
972972
| (
973973
Fact::DynamicRange {
974974
bit_width: bw_dynamic,
975-
min: ref min_dynamic,
976-
max: ref max_dynamic,
975+
min: min_dynamic,
976+
max: max_dynamic,
977977
},
978978
Fact::Range {
979979
bit_width: bw_static,
@@ -1070,16 +1070,16 @@ impl<'a> FactContext<'a> {
10701070
},
10711071
Fact::DynamicMem {
10721072
ty,
1073-
min: ref min_dynamic,
1074-
max: ref max_dynamic,
1073+
min: min_dynamic,
1074+
max: max_dynamic,
10751075
nullable,
10761076
},
10771077
)
10781078
| (
10791079
Fact::DynamicMem {
10801080
ty,
1081-
min: ref min_dynamic,
1082-
max: ref max_dynamic,
1081+
min: min_dynamic,
1082+
max: max_dynamic,
10831083
nullable,
10841084
},
10851085
Fact::Range {

‎cranelift/codegen/src/isa/aarch64/abi.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1036,12 +1036,12 @@ impl ABIMachineSpec for AArch64MachineDeps {
10361036

10371037
fn gen_call(dest: &CallDest, tmp: Writable<Reg>, info: CallInfo<()>) -> SmallVec<[Inst; 2]> {
10381038
let mut insts = SmallVec::new();
1039-
match &dest {
1040-
&CallDest::ExtName(ref name, RelocDistance::Near) => {
1039+
match dest {
1040+
CallDest::ExtName(name, RelocDistance::Near) => {
10411041
let info = Box::new(info.map(|()| name.clone()));
10421042
insts.push(Inst::Call { info });
10431043
}
1044-
&CallDest::ExtName(ref name, RelocDistance::Far) => {
1044+
CallDest::ExtName(name, RelocDistance::Far) => {
10451045
insts.push(Inst::LoadExtName {
10461046
rd: tmp,
10471047
name: Box::new(name.clone()),
@@ -1050,7 +1050,7 @@ impl ABIMachineSpec for AArch64MachineDeps {
10501050
let info = Box::new(info.map(|()| tmp.to_reg()));
10511051
insts.push(Inst::CallInd { info });
10521052
}
1053-
&CallDest::Reg(reg) => {
1053+
CallDest::Reg(reg) => {
10541054
let info = Box::new(info.map(|()| *reg));
10551055
insts.push(Inst::CallInd { info });
10561056
}

‎cranelift/codegen/src/isa/riscv64/abi.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -558,11 +558,11 @@ impl ABIMachineSpec for Riscv64MachineDeps {
558558
fn gen_call(dest: &CallDest, tmp: Writable<Reg>, info: CallInfo<()>) -> SmallVec<[Self::I; 2]> {
559559
let mut insts = SmallVec::new();
560560
match &dest {
561-
&CallDest::ExtName(ref name, RelocDistance::Near) => {
561+
CallDest::ExtName(name, RelocDistance::Near) => {
562562
let info = Box::new(info.map(|()| name.clone()));
563563
insts.push(Inst::Call { info })
564564
}
565-
&CallDest::ExtName(ref name, RelocDistance::Far) => {
565+
CallDest::ExtName(name, RelocDistance::Far) => {
566566
insts.push(Inst::LoadExtName {
567567
rd: tmp,
568568
name: Box::new(name.clone()),
@@ -571,7 +571,7 @@ impl ABIMachineSpec for Riscv64MachineDeps {
571571
let info = Box::new(info.map(|()| tmp.to_reg()));
572572
insts.push(Inst::CallInd { info });
573573
}
574-
&CallDest::Reg(reg) => {
574+
CallDest::Reg(reg) => {
575575
let info = Box::new(info.map(|()| *reg));
576576
insts.push(Inst::CallInd { info });
577577
}

‎cranelift/codegen/src/isa/riscv64/inst/mod.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -1588,8 +1588,8 @@ impl Inst {
15881588
eew,
15891589
to,
15901590
from,
1591-
ref mask,
1592-
ref vstate,
1591+
mask,
1592+
vstate,
15931593
..
15941594
} => {
15951595
let base = format_vec_amode(from);
@@ -1602,8 +1602,8 @@ impl Inst {
16021602
eew,
16031603
to,
16041604
from,
1605-
ref mask,
1606-
ref vstate,
1605+
mask,
1606+
vstate,
16071607
..
16081608
} => {
16091609
let dst = format_vec_amode(to);

‎cranelift/codegen/src/isa/x64/inst/args.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -505,7 +505,7 @@ impl PrettyPrint for Amode {
505505
pretty_print_reg(index.to_reg(), 8),
506506
1 << shift
507507
),
508-
Amode::RipRelative { ref target } => format!("label{}(%rip)", target.get()),
508+
Amode::RipRelative { target } => format!("label{}(%rip)", target.get()),
509509
}
510510
}
511511
}

‎cranelift/codegen/src/isa/x64/inst/emit.rs

Lines changed: 4 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -4517,7 +4517,7 @@ pub(crate) fn emit(
45174517
}
45184518
}
45194519

4520-
Inst::ElfTlsGetAddr { ref symbol, dst } => {
4520+
Inst::ElfTlsGetAddr { symbol, dst } => {
45214521
let dst = dst.to_reg().to_reg();
45224522
debug_assert_eq!(dst, regs::rax());
45234523

@@ -4546,7 +4546,7 @@ pub(crate) fn emit(
45464546
sink.put4(0); // offset
45474547
}
45484548

4549-
Inst::MachOTlsGetAddr { ref symbol, dst } => {
4549+
Inst::MachOTlsGetAddr { symbol, dst } => {
45504550
let dst = dst.to_reg().to_reg();
45514551
debug_assert_eq!(dst, regs::rax());
45524552

@@ -4562,11 +4562,7 @@ pub(crate) fn emit(
45624562
sink.put1(0x17);
45634563
}
45644564

4565-
Inst::CoffTlsGetAddr {
4566-
ref symbol,
4567-
dst,
4568-
tmp,
4569-
} => {
4565+
Inst::CoffTlsGetAddr { symbol, dst, tmp } => {
45704566
let dst = dst.to_reg().to_reg();
45714567
debug_assert_eq!(dst, regs::rax());
45724568

@@ -4619,7 +4615,7 @@ pub(crate) fn emit(
46194615
sink.put4(0); // offset
46204616
}
46214617

4622-
Inst::Unwind { ref inst } => {
4618+
Inst::Unwind { inst } => {
46234619
sink.add_unwind(inst.clone());
46244620
}
46254621

‎cranelift/codegen/src/isa/x64/inst/mod.rs

Lines changed: 3 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -1923,21 +1923,17 @@ impl PrettyPrint for Inst {
19231923

19241924
Inst::Ud2 { trap_code } => format!("ud2 {trap_code}"),
19251925

1926-
Inst::ElfTlsGetAddr { ref symbol, dst } => {
1926+
Inst::ElfTlsGetAddr { symbol, dst } => {
19271927
let dst = pretty_print_reg(dst.to_reg().to_reg(), 8);
19281928
format!("{dst} = elf_tls_get_addr {symbol:?}")
19291929
}
19301930

1931-
Inst::MachOTlsGetAddr { ref symbol, dst } => {
1931+
Inst::MachOTlsGetAddr { symbol, dst } => {
19321932
let dst = pretty_print_reg(dst.to_reg().to_reg(), 8);
19331933
format!("{dst} = macho_tls_get_addr {symbol:?}")
19341934
}
19351935

1936-
Inst::CoffTlsGetAddr {
1937-
ref symbol,
1938-
dst,
1939-
tmp,
1940-
} => {
1936+
Inst::CoffTlsGetAddr { symbol, dst, tmp } => {
19411937
let dst = pretty_print_reg(dst.to_reg().to_reg(), 8);
19421938
let tmp = tmp.to_reg().to_reg();
19431939

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