Merge pull request #1659 from diffblue/parameter_vs_typedef

KNOWNBUG test for a parameter that hides a typedef

Author: tautschnig

regression/verilog/parameters/parameter_vs_typedef.desc

@@ -0,0 +1,9 @@
+KNOWNBUG
+parameter_vs_typedef.sv
+
+^EXIT=0$
+^SIGNAL=0$
+--
+^warning: ignoring
+--
+This does not parse.

regression/verilog/parameters/parameter_vs_typedef.sv

@@ -0,0 +1,6 @@
+typedef int some_identifier;
+
+module main;
+  parameter some_identifier = 123;
+  assert final(some_identifier == 123);
+endmodule