SystemVerilog: non-wildcard imports

This adds 1800 2017 26.3 non-wildcard import declarations.

Author: kroening

regression/verilog/packages/import2.desc

@@ -1,8 +1,7 @@
-KNOWNBUG
+CORE
 import2.sv
 --bound 0
 ^EXIT=0$
 ^SIGNAL=0$
 --
 --
-The identifier is not found.

regression/verilog/packages/import3.desc

@@ -0,0 +1,7 @@
+CORE
+import3.sv
+--bound 0
+^EXIT=0$
+^SIGNAL=0$
+--
+--

regression/verilog/packages/import3.sv

@@ -0,0 +1,8 @@
+package my_pkg;
+  typedef int my_type;
+endpackage
+
+module main;
+  import my_pkg::my_type;
+  assert final($typename(my_type) == "int");
+endmodule

src/verilog/parser.y

@@ -1488,8 +1488,10 @@ package_import_item:
           package_identifier "::" identifier
                 { init($$, ID_verilog_import_item);
                   auto package_base_name = stack_expr($1).get(ID_base_name);
+                  auto identifier_base_name = stack_expr($3).get(ID_base_name);
                   stack_expr($$).set(ID_verilog_package, package_base_name);
-                  stack_expr($$).set(ID_base_name, stack_expr($3).id()); }
+                  stack_expr($$).set(ID_base_name, identifier_base_name);
+                  PARSER.scopes.import(package_base_name, identifier_base_name); }
         | package_identifier "::" "*"
                 { init($$, ID_verilog_import_item);
                   auto package_base_name = stack_expr($1).get(ID_base_name);
@@ -2010,6 +2012,7 @@ list_of_param_assignments:
 param_assignment: param_identifier '=' constant_param_expression
                 { init($$, ID_parameter);
                   auto base_name = stack_expr($1).get(ID_base_name);
+                  PARSER.scopes.add_name(base_name, "", verilog_scopet::PARAMETER);
                   stack_expr($$).set(ID_base_name, base_name);
                   addswap($$, ID_value, $3); }
         ;

src/verilog/scanner.l

@@ -77,13 +77,15 @@ YYSTYPE make_identifier(irep_idt base_name, exprt &dest)
   else
   {
     dest.set(ID_scope, scope_ptr->prefix);
+    if(!scope_ptr->import.empty())
+      dest.set("import", scope_ptr->import);
     return scope_ptr->identifier_token();
   }
 }
 
 #define IDENTIFIER(text) \
   { newstack(yyveriloglval); \
-    auto base_name = text; /* hashing here */ \
+    irep_idt base_name = text; /* hashing here */ \
     return make_identifier(base_name, stack_expr(yyveriloglval)); \
   }
 #define KEYWORD(s, x) \

src/verilog/verilog_elaborate_type.cpp

@@ -343,7 +343,21 @@ typet verilog_typecheck_exprt::elaborate_type(const typet &src)
   {
     // Look it up!
     auto base_name = to_verilog_typedef_type(src).base_name();
-    const auto *symbol_ptr = resolve(base_name);
+    const symbolt *symbol_ptr;
+    auto import = src.get("import");
+    if(import != irep_idt{})
+    {
+      auto full_identifier = "Verilog::package::" + id2string(import);
+
+      if(ns.lookup(full_identifier, symbol_ptr))
+      {
+        DATA_INVARIANT(false, "failed to find imported typedef identifier");
+      }
+    }
+    else
+    {
+      symbol_ptr = resolve(base_name);
+    }
 
     if(symbol_ptr == nullptr)
       throw errort().with_location(source_location)

src/verilog/verilog_scope.cpp

@@ -52,6 +52,7 @@ unsigned verilog_scopet::identifier_token() const
   case verilog_scopet::TASK:            return TOK_NON_TYPE_IDENTIFIER;
   case verilog_scopet::FUNCTION:        return TOK_NON_TYPE_IDENTIFIER;
   case verilog_scopet::TYPEDEF:         return TOK_TYPE_IDENTIFIER;
+  case verilog_scopet::PARAMETER:       return TOK_NON_TYPE_IDENTIFIER;
   case verilog_scopet::PROPERTY:        return TOK_NON_TYPE_IDENTIFIER;
   case verilog_scopet::SEQUENCE:        return TOK_NON_TYPE_IDENTIFIER;
   case verilog_scopet::OTHER:           return TOK_NON_TYPE_IDENTIFIER;
@@ -61,6 +62,25 @@ unsigned verilog_scopet::identifier_token() const
   UNREACHABLE;
 }
 
+void verilog_scopest::import(irep_idt package, irep_idt base_name)
+{
+  // find the package in the global scope
+  auto package_it = top_scope.scope_map.find(package);
+  if(package_it == top_scope.scope_map.end())
+    return;
+
+  // find the identifier in the package
+  auto name_it = package_it->second.scope_map.find(base_name);
+  if(name_it != package_it->second.scope_map.end())
+  {
+    auto &scope = add_name(base_name, "", name_it->second.kind);
+    scope.import = name_it->second.identifier();
+  }
+  else
+  {
+  }
+}
+
 void verilog_scopest::enter_package_scope(irep_idt base_name)
 {
   // look in the global scope

src/verilog/verilog_scope.h

@@ -29,6 +29,7 @@ struct verilog_scopet
     FUNCTION,
     BLOCK,
     TYPEDEF,
+    PARAMETER,
     PROPERTY,
     SEQUENCE,
     OTHER
@@ -54,6 +55,7 @@ struct verilog_scopet
   irep_idt __base_name;
   std::string prefix;
   kindt kind;
+  irep_idt import;
 
   irep_idt identifier() const
   {
@@ -132,6 +134,8 @@ class verilog_scopest
     scope_stack.pop_back();
   }
 
+  void import(irep_idt package, irep_idt base_name);
+
   // Look up an identifier, starting from the current scope,
   // going upwards until found. Returns nullptr when not found.
   const scopet *lookup(irep_idt base_name) const;

src/verilog/verilog_typecheck_expr.cpp

@@ -1383,8 +1383,23 @@ exprt verilog_typecheck_exprt::convert_verilog_identifier(
   verilog_identifier_exprt expr,
   const std::optional<typet> &implicit_net_type)
 {
+  const symbolt *symbol;
   auto base_name = expr.base_name();
-  auto symbol = resolve(base_name);
+  auto import = expr.get("import");
+
+  if(import != irep_idt{})
+  {
+    auto full_identifier = "Verilog::package::" + id2string(import);
+
+    if(ns.lookup(full_identifier, symbol))
+    {
+      DATA_INVARIANT(false, "failed to find imported identifier");
+    }
+  }
+  else
+  {
+    symbol = resolve(base_name);
+  }
 
   if(symbol != nullptr)
   {