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19 | 19 | ethernet0 = ð1; |
20 | 20 | ethernet1 = ð2; |
21 | 21 | serial0 = &uart5; |
| 22 | + i2c2 = &i2c2; |
| 23 | + i2c3 = &i2c3; |
22 | 24 | }; |
23 | 25 |
|
24 | 26 | chosen { |
|
125 | 127 | phy0_eth2: ethernet-phy@0 { |
126 | 128 | reg = <0>; |
127 | 129 | compatible = "ethernet-phy-id0007.c0f0"; /* PHY ID for SMSC LAN8720Ai */ |
128 | | - reset-gpios = <&gpioi 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
| 130 | + reset-gpios = <&gpioh 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
129 | 131 | }; |
130 | 132 | }; |
131 | 133 | }; |
132 | 134 |
|
133 | | -&i2c1 { |
| 135 | +&i2c2 { |
134 | 136 | pinctrl-names = "default", "sleep"; |
135 | | - pinctrl-0 = <&i2c1_pins_a>; |
136 | | - pinctrl-1 = <&i2c1_sleep_pins_a>; |
137 | | - i2c-scl-rising-time-ns = <96>; |
138 | | - i2c-scl-falling-time-ns = <3>; |
139 | | - clock-frequency = <1000000>; |
| 137 | + pinctrl-0 = <&ccmp13_i2c2_pins_a>; |
| 138 | + pinctrl-1 = <&ccmp13_i2c2_sleep_pins_a>; |
| 139 | + i2c-scl-rising-time-ns = <170>; |
| 140 | + i2c-scl-falling-time-ns = <5>; |
| 141 | + clock-frequency = <400000>; |
140 | 142 | status = "okay"; |
141 | 143 | /* spare dmas for other usage */ |
142 | 144 | /delete-property/dmas; |
143 | 145 | /delete-property/dma-names; |
144 | 146 | }; |
145 | 147 |
|
146 | | -&i2c5 { |
| 148 | +&i2c3 { |
147 | 149 | pinctrl-names = "default", "sleep"; |
148 | | - pinctrl-0 = <&i2c5_pins_a>; |
149 | | - pinctrl-1 = <&i2c5_sleep_pins_a>; |
| 150 | + pinctrl-0 = <&ccmp13_i2c3_pins_a>; |
| 151 | + pinctrl-1 = <&ccmp13_i2c3_sleep_pins_a>; |
150 | 152 | i2c-scl-rising-time-ns = <170>; |
151 | 153 | i2c-scl-falling-time-ns = <5>; |
152 | 154 | clock-frequency = <400000>; |
153 | | - status = "disabled"; |
| 155 | + status = "okay"; |
154 | 156 | /* spare dmas for other usage */ |
155 | 157 | /delete-property/dmas; |
156 | 158 | /delete-property/dma-names; |
|
299 | 301 | }; |
300 | 302 |
|
301 | 303 | &usbotg_hs { |
| 304 | + u-boot,force-b-session-valid; |
| 305 | + dr_mode = "peripheral"; |
302 | 306 | phys = <&usbphyc_port1 0>; |
303 | 307 | phy-names = "usb2-phy"; |
304 | 308 | usb-role-switch; |
|
347 | 351 | }; |
348 | 352 |
|
349 | 353 | &pinctrl { |
| 354 | + ccmp13_i2c2_pins_a: ccmp13_i2c2-0 { |
| 355 | + pins { |
| 356 | + pinmux = <STM32_PINMUX('F', 2, AF4)>, /* I2C2_SCL */ |
| 357 | + <STM32_PINMUX('F', 1, AF4)>; /* I2C2_SDA */ |
| 358 | + bias-disable; |
| 359 | + drive-open-drain; |
| 360 | + slew-rate = <0>; |
| 361 | + }; |
| 362 | + }; |
| 363 | + |
| 364 | + ccmp13_i2c2_sleep_pins_a: ccmp13_i2c2-sleep-0 { |
| 365 | + pins { |
| 366 | + pinmux = <STM32_PINMUX('F', 2, ANALOG)>, /* I2C2_SCL */ |
| 367 | + <STM32_PINMUX('F', 1, ANALOG)>; /* I2C2_SDA */ |
| 368 | + }; |
| 369 | + }; |
| 370 | + |
| 371 | + ccmp13_i2c3_pins_a: ccmp13_i2c3-0 { |
| 372 | + pins { |
| 373 | + pinmux = <STM32_PINMUX('B', 8, AF5)>, /* I2C3_SCL */ |
| 374 | + <STM32_PINMUX('H', 14, AF4)>; /* I2C3_SDA */ |
| 375 | + bias-disable; |
| 376 | + drive-open-drain; |
| 377 | + slew-rate = <0>; |
| 378 | + }; |
| 379 | + }; |
| 380 | + |
| 381 | + ccmp13_i2c3_sleep_pins_a: ccmp13_i2c3-sleep-0 { |
| 382 | + pins { |
| 383 | + pinmux = <STM32_PINMUX('B', 8, ANALOG)>, /* I2C3_SCL */ |
| 384 | + <STM32_PINMUX('H', 14, ANALOG)>; /* I2C3_SDA */ |
| 385 | + }; |
| 386 | + }; |
| 387 | + |
350 | 388 | ccmp13_eth1_rgmii_pins: ccmp13-eth1-rgmii-1 { |
351 | 389 | pins1 { |
352 | 390 | pinmux = <STM32_PINMUX('F', 12, AF11)>, /* ETH1_CLK125 */ |
|
402 | 440 | pins1 { |
403 | 441 | pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH2_TXD0 */ |
404 | 442 | <STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */ |
405 | | - <STM32_PINMUX('H', 11, AF11)>, /* ETH2_REF_CLK */ |
| 443 | + <STM32_PINMUX('A', 11, AF13)>, /* ETH2_CLK */ |
406 | 444 | <STM32_PINMUX('F', 6, AF11)>, /* ETH2_TX_EN */ |
407 | 445 | <STM32_PINMUX('B', 2, AF11)>, /* ETH2_MDIO */ |
408 | 446 | <STM32_PINMUX('G', 5, AF10)>; /* ETH2_MDC */ |
|
414 | 452 | pins2 { |
415 | 453 | pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH2_RXD0 */ |
416 | 454 | <STM32_PINMUX('E', 2, AF10)>, /* ETH2_RXD1 */ |
417 | | - <STM32_PINMUX('A', 12, AF11)>; /* ETH2_RX_DV */ |
| 455 | + <STM32_PINMUX('A', 12, AF11)>, /* ETH2_RX_DV */ |
| 456 | + <STM32_PINMUX('F', 11, AF12)>; /* ETH2_RX_ER */ |
418 | 457 | bias-disable; |
419 | 458 | }; |
420 | 459 | }; |
|
423 | 462 | pins1 { |
424 | 463 | pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH2_TXD0 */ |
425 | 464 | <STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */ |
426 | | - <STM32_PINMUX('H', 11, ANALOG)>, /* ETH2_REF_CLK */ |
| 465 | + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH2_CLK */ |
427 | 466 | <STM32_PINMUX('F', 6, ANALOG)>, /* ETH2_TX_EN */ |
428 | 467 | <STM32_PINMUX('B', 2, ANALOG)>, /* ETH2_MDIO */ |
429 | 468 | <STM32_PINMUX('G', 5, ANALOG)>, /* ETH2_MDC */ |
430 | 469 | <STM32_PINMUX('F', 4, ANALOG)>, /* ETH2_RXD0 */ |
431 | 470 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH2_RXD1 */ |
432 | | - <STM32_PINMUX('A', 12, ANALOG)>; /* ETH2_RX_DV */ |
| 471 | + <STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_DV */ |
| 472 | + <STM32_PINMUX('F', 11, ANALOG)>; /* ETH2_RX_ER */ |
433 | 473 | }; |
434 | 474 | }; |
435 | 475 |
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