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127 | 127 | phy0_eth2: ethernet-phy@0 { |
128 | 128 | reg = <0>; |
129 | 129 | compatible = "ethernet-phy-id0007.c0f0"; /* PHY ID for SMSC LAN8720Ai */ |
130 | | - reset-gpios = <&gpioi 2 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
| 130 | + reset-gpios = <&gpioh 7 (GPIO_ACTIVE_LOW | GPIO_PULL_UP)>; |
131 | 131 | }; |
132 | 132 | }; |
133 | 133 | }; |
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440 | 440 | pins1 { |
441 | 441 | pinmux = <STM32_PINMUX('F', 7, AF11)>, /* ETH2_TXD0 */ |
442 | 442 | <STM32_PINMUX('G', 11, AF10)>, /* ETH2_TXD1 */ |
443 | | - <STM32_PINMUX('H', 11, AF11)>, /* ETH2_REF_CLK */ |
| 443 | + <STM32_PINMUX('A', 11, AF13)>, /* ETH2_CLK */ |
444 | 444 | <STM32_PINMUX('F', 6, AF11)>, /* ETH2_TX_EN */ |
445 | 445 | <STM32_PINMUX('B', 2, AF11)>, /* ETH2_MDIO */ |
446 | 446 | <STM32_PINMUX('G', 5, AF10)>; /* ETH2_MDC */ |
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452 | 452 | pins2 { |
453 | 453 | pinmux = <STM32_PINMUX('F', 4, AF11)>, /* ETH2_RXD0 */ |
454 | 454 | <STM32_PINMUX('E', 2, AF10)>, /* ETH2_RXD1 */ |
455 | | - <STM32_PINMUX('A', 12, AF11)>; /* ETH2_RX_DV */ |
| 455 | + <STM32_PINMUX('A', 12, AF11)>, /* ETH2_RX_DV */ |
| 456 | + <STM32_PINMUX('F', 11, AF12)>; /* ETH2_RX_ER */ |
456 | 457 | bias-disable; |
457 | 458 | }; |
458 | 459 | }; |
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461 | 462 | pins1 { |
462 | 463 | pinmux = <STM32_PINMUX('F', 7, ANALOG)>, /* ETH2_TXD0 */ |
463 | 464 | <STM32_PINMUX('G', 11, ANALOG)>, /* ETH2_TXD1 */ |
464 | | - <STM32_PINMUX('H', 11, ANALOG)>, /* ETH2_REF_CLK */ |
| 465 | + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH2_CLK */ |
465 | 466 | <STM32_PINMUX('F', 6, ANALOG)>, /* ETH2_TX_EN */ |
466 | 467 | <STM32_PINMUX('B', 2, ANALOG)>, /* ETH2_MDIO */ |
467 | 468 | <STM32_PINMUX('G', 5, ANALOG)>, /* ETH2_MDC */ |
468 | 469 | <STM32_PINMUX('F', 4, ANALOG)>, /* ETH2_RXD0 */ |
469 | 470 | <STM32_PINMUX('E', 2, ANALOG)>, /* ETH2_RXD1 */ |
470 | | - <STM32_PINMUX('A', 12, ANALOG)>; /* ETH2_RX_DV */ |
| 471 | + <STM32_PINMUX('A', 12, ANALOG)>, /* ETH2_RX_DV */ |
| 472 | + <STM32_PINMUX('F', 11, ANALOG)>; /* ETH2_RX_ER */ |
471 | 473 | }; |
472 | 474 | }; |
473 | 475 |
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