Control Code Generator [CCG] Optimization

[command-paul]

Code Cleanup logs

[vedantcj]

Bits to Eliminate:

CCG1:

• X2SP

CCG2:

• EFL(always 0)
• LSP

CCG3:

• BB

CCG4:

• FLRN
• EFL(always 0)

Bits to pass on:

CCG1:

• None

CCG2:

• ERN from CCG1(ERN)
• SOD from CCG1(XSOD)
• ESP from CCG1(ESP)

CCG3:

• None

CCG4:

• WR from CCG2(XWR)
• LRN from CCG2(XRN)
• LR0 from CCG2(XR0)
• ERN from CCG2(ERN from CCG1(ERN))
• ISP from CCG2(ISP)

[command-paul]

Day 3 :: Tasks Accomplished & ToDo

Module Interface I/O Elaboration

• Top Module
• Alu - ALUModule (ALUModule.v),
• As1 - AddressSelector1 (as1.v),
• As2 - AddressSelector2 (as2.v),
• Bbl - Bubble (Bubble.v),
• Buf12 - Buffer1 (Buffer1.v),
• Buf23 - Buffer2 (Buffer2.v),
• Buf34 - Buffer3 (Buffer3.v),
• CndBr - ConditionalBranch (ConditionalBranch.v)
• CCGA1 - ControlCodeGenerator1Async (ControlCodeGenerator1Async.v),
• CCG2 - ControlCodeGenerator2 (ControlCodeGenerator2.v),
• CCG3 - ControlCodeGenerator3 (ControlCodeGenerator3.v),
• CCG4 - ControlCodeGenerator4 (ControlCodeGenerator4.v),
• FlReg - FlagRegister (FlagRegister.v),
• WBMod - WBModule (WBModule.v),
• IO - Io_GPIB (IO_Module.v),
• RegArr - RegisterArray (RegisterArr.v),
• RegFl - RegisterFlags (RegisterFlags.v),
• StkPtr - StackPointer (StackPointer.v),
• PrgCtr - ProgramCounter (pc.v),
• OprDc1 - OperandDecode1 (OperandDecode2.v),
• OprDc2 - OperandDecode2 (OperandDecode2.v),
• MultPrtMem - MultiPortMem (3PortMem.v),
• InstReg - IR (IR.v)

ToDo

• Resolve File Operand Decode 2 Naming Conflict

[niladut]

Wire Documentation

Format

// <FromModule.Port> to <ToModule.Port>

Top Module

• Unused Wires Removed
• Comment wire routing: TO and FROM modules/ports

Port Documentation

Comment Format

// Input/Output :: Signal generating / Receiving module :: Name of the signal inside the receiving module

Modules Commented

• Top Module

[PrasannaNatarajan]

• Changed git repository to only source code
• Commenting Modules yet to complete

[command-paul]

Commenting Top_Module - Module Instantiations complete

[AbhimanyuChoudhury]

Verified new cleaned up version against initial version.

[AbhimanyuChoudhury]

Modules expanded to 16-bit

• 3PortMem
• ALUbasic
• ALUModule
• as1
• as2
• Bubble
• Buffer1
• Buffer2
• Buffer3
• ConditionalBranch
• ControlCodeGenerator1Async
• ControlCodeGenerator2
• ControlCodeGenerator3
• ControlCodeGenerator4
• FlagRegister
• IO_Module
• IR
• OperandDecode1
• OperandDecode2
• pc
• RegisterArr
• RegisterFlags
• StackPointer
• TopModule
• WBModule