add better f-string support for sim

Author: hexdae

Cargo.lock

@@ -11,11 +11,11 @@ authors = ["Diode Computers, Inc. <founders@diode.computer>"]
 
 [workspace.dependencies]
 glam = "0.31.0"
-starlark = { git = "https://github.com/diodeinc/starlark-rust", rev = "e80bd650" }
-starlark_map = { git = "https://github.com/diodeinc/starlark-rust", rev = "e80bd650" }
-starlark_derive = { git = "https://github.com/diodeinc/starlark-rust", rev = "e80bd650" }
-starlark_syntax = { git = "https://github.com/diodeinc/starlark-rust", rev = "e80bd650" }
-allocative = { git = "https://github.com/diodeinc/starlark-rust", rev = "e80bd650" }
+starlark = { git = "https://github.com/diodeinc/starlark-rust", rev = "bd12784d" }
+starlark_map = { git = "https://github.com/diodeinc/starlark-rust", rev = "bd12784d" }
+starlark_derive = { git = "https://github.com/diodeinc/starlark-rust", rev = "bd12784d" }
+starlark_syntax = { git = "https://github.com/diodeinc/starlark-rust", rev = "bd12784d" }
+allocative = { git = "https://github.com/diodeinc/starlark-rust", rev = "bd12784d" }
 
 ruff_python_formatter = { git = "https://github.com/astral-sh/ruff", tag = "0.13.0" }
 ruff_formatter = { git = "https://github.com/astral-sh/ruff", tag = "0.13.0" }

Cargo.toml

@@ -163,11 +163,7 @@ where
 
 impl<'v, V: ValueLike<'v>> std::fmt::Display for NetValueGen<V> {
     fn fmt(&self, f: &mut std::fmt::Formatter<'_>) -> std::fmt::Result {
-        write!(
-            f,
-            "{}(name: {:?}, id: {:?})",
-            self.type_name, self.name, self.net_id
-        )
+        write!(f, "{}", self.name)
     }
 }
 

crates/pcb-zen-core/src/lang/net.rs

@@ -16,12 +16,12 @@ expression: snapshot_output
     )
   )
 )
-Error: Input 'signal' (type) has wrong type for this placeholder: expected Net, got SingleNet(signal=Net(name: "SIG_signal", id: <ID>))
+Error: Input 'signal' (type) has wrong type for this placeholder: expected Net, got SingleNet(signal=SIG_signal)
    ╭─[ [TEMP_DIR]child.zen:2:10 ]
    │
  2 │ signal = io("signal", Net)
    │          ────────┬────────  
-   │                  ╰────────── Input 'signal' (type) has wrong type for this placeholder: expected Net, got SingleNet(signal=Net(name: "SIG_signal", id: <ID>))
+   │                  ╰────────── Input 'signal' (type) has wrong type for this placeholder: expected Net, got SingleNet(signal=SIG_signal)
    │
    ├─[ [TEMP_DIR]parent.zen:8:1 ]
    │