updated tests and formatting

Author: djcopley

.library_mapping.xml

@@ -3,23 +3,23 @@ use ieee.std_logic_1164.all;
 use ieee.numeric_std.all;
 
 entity vga is
-  port(
-	  clk : in std_logic; -- Pixel clock
-	  rst : in std_logic;
-
-    hsync : out std_logic;
-    vsync : out std_logic;
-
-    -- Input colors
-    i_red : in std_logic_vector(1 downto 0);
-    i_blue : in std_logic_vector(1 downto 0);
-    i_green : in std_logic_vector(1 downto 0);
-
-    -- Output colors
-    -- 4 x 4 x 4 yields 64 different colors
-    o_red : out std_logic_vector(1 downto 0);
-    o_blue : out std_logic_vector(1 downto 0);
-    o_green : out std_logic_vector(1 downto 0)
+    port(
+        clk : in std_logic;
+        rst : in std_logic;
+
+        hsync : out std_logic;
+        vsync : out std_logic;
+
+        -- Input colors
+        i_red : in std_logic_vector(1 downto 0);
+        i_blue : in std_logic_vector(1 downto 0);
+        i_green : in std_logic_vector(1 downto 0);
+    
+        -- Output colors
+        -- 4 x 4 x 4 yields 64 different colors
+        o_red : out std_logic_vector(1 downto 0);
+        o_blue : out std_logic_vector(1 downto 0);
+        o_green : out std_logic_vector(1 downto 0)
   );
 end entity vga;
 
@@ -69,13 +69,13 @@ architecture RTL of vga is
 
 begin
 
-	process(clk)
+  process(clk)
 
     variable wrapped : boolean;
 
   begin
 
-		if rising_edge(clk) then
+    if rising_edge(clk) then
 
       if rst='1' then
 
@@ -118,7 +118,7 @@ begin
 
       end if;
 
-		end if;
+    end if;
 
-	end process;
+  end process;
 end architecture RTL;

.project

@@ -10,21 +10,24 @@ architecture rtl of vga_tb is
   -- Clock
   constant CLOCK_SPEED : natural := 65e6;
   constant CLOCK_PERIOD : time := 1.0 sec / CLOCK_SPEED;
-  constant DUTY_CYCLE : real := 0.5;
+  constant CLOCK_DUTY : real := 0.5;
+  constant CLOCK_PHASE : real := 0.0 / 360.0;
+
+  constant RESET_PERIOD : time := 10 us;
 
   signal clk : std_logic := '0';
   signal rst : std_logic := '0';
 
   signal hsync, vsync : std_logic;
 
-  signal o_red, o_blue, o_green : std_logic_vector(2 downto 0);
+  signal o_red, o_blue, o_green : std_logic_vector(1 downto 0);
 
 begin
 
   vga1 : entity work.vga 
     port map(
-       	clk => clk, -- Pixel clock
-		rst => rst,
+       	clk => clk,
+        rst => rst,
 
         hsync => hsync,
         vsync => vsync,
@@ -41,8 +44,18 @@ begin
         o_green => o_green 
     );
 
-
-  clk <= not clk after CLOCK_PERIOD / 2;
+  clk_gen : process
+  begin
+    clk <= transport '1' after (CLOCK_PERIOD * CLOCK_PHASE);
+    clk <= transport '0' after (CLOCK_PERIOD * (CLOCK_DUTY + CLOCK_PHASE));
+    wait for CLOCK_PERIOD;
+  end process;
+
+  reset : process
+  begin
+    rst <= '1', '0' after RESET_PERIOD;
+    wait;
+  end process;
 
   end architecture rtl;