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‎.gitignore‎

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vhdltool-config.yaml
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‎.library_mapping.xml‎

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<?xml version="1.0" encoding="UTF-8"?>
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<com.sigasi.hdt.shared.librarymapping.model:LibraryMappings xmlns:com.sigasi.hdt.shared.librarymapping.model="com.sigasi.hdt.vhdl.scoping.librarymapping" Version="2">
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<Mappings Location="Common Libraries/IEEE" Library="ieee"/>
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<Mappings Location="Common Libraries/IEEE Synopsys" Library="ieee"/>
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<Mappings Location="Common Libraries" Library="not mapped"/>
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<Mappings Location="Common Libraries/STD" Library="std"/>
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<Mappings Location="" Library="work"/>
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</com.sigasi.hdt.shared.librarymapping.model:LibraryMappings>

‎.project‎

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<?xml version="1.0" encoding="UTF-8"?>
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<projectDescription>
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<name>VGA</name>
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<comment></comment>
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<projects>
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</projects>
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<buildSpec>
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<buildCommand>
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<name>org.eclipse.xtext.ui.shared.xtextBuilder</name>
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<arguments>
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</arguments>
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</buildCommand>
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</buildSpec>
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<natures>
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<nature>com.sigasi.hdt.vhdl.ui.vhdlNature</nature>
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<nature>org.eclipse.xtext.ui.shared.xtextNature</nature>
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</natures>
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<linkedResources>
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<link>
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<name>Common Libraries</name>
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<type>2</type>
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<locationURI>virtual:/virtual</locationURI>
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</link>
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<link>
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<name>Common Libraries/DRAG_REUSABLE_LIBRARIES_HERE.txt</name>
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<type>1</type>
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<locationURI>sigasiresource:/vhdl/readme.txt</locationURI>
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</link>
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<link>
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<name>Common Libraries/IEEE</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/IEEE</locationURI>
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</link>
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<link>
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<name>Common Libraries/IEEE Synopsys</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/IEEE%20Synopsys</locationURI>
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</link>
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<link>
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<name>Common Libraries/STD</name>
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<type>2</type>
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<locationURI>sigasiresource:/vhdl/93/STD</locationURI>
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</link>
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</linkedResources>
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</projectDescription>

‎.settings/com.sigasi.hdt.vhdl.version.prefs‎

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<project>=93

‎.settings/org.eclipse.core.resources.prefs‎

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eclipse.preferences.version=1
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encoding//Common\ Libraries/IEEE=utf-8
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encoding//Common\ Libraries/IEEE\ Synopsys=utf-8
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encoding//Common\ Libraries/STD=utf-8
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encoding/Common\ Libraries=utf-8

‎src/vga.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga is
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port(
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clk : in std_logic; -- Pixel clock
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rst : in std_logic;
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hsync : out std_logic;
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vsync : out std_logic;
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-- Input colors
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i_red : in std_logic_vector(1 downto 0);
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i_blue : in std_logic_vector(1 downto 0);
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i_green : in std_logic_vector(1 downto 0);
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-- Output colors
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-- 4 x 4 x 4 yields 64 different colors
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o_red : out std_logic_vector(1 downto 0);
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o_blue : out std_logic_vector(1 downto 0);
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o_green : out std_logic_vector(1 downto 0)
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);
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end entity vga;
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architecture RTL of vga is
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-- Timing - 1024 x 768 @ 60Hz
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-- 65 MHz Pixel Clock
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constant H_VISIBLE_AREA : natural := 1024;
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constant H_FRONT_PORCH : natural := H_VISIBLE_AREA + 0;
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constant H_SYNC_PULSE : natural := H_FRONT_PORCH + 24;
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constant H_BACK_PORCH : natural := H_SYNC_PULSE + 136;
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constant H_WHOLE_LINE : natural := H_BACK_PORCH + 160;
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constant V_VISIBLE_AREA : natural := 768;
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constant V_FRONT_PORCH : natural := V_VISIBLE_AREA + 0;
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constant V_SYNC_PULSE : natural := V_FRONT_PORCH + 3;
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constant V_BACK_PORCH : natural := V_SYNC_PULSE + 6;
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constant V_WHOLE_LINE : natural := V_BACK_PORCH + 29;
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-- Data for test
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constant WHITE_PIXEL : std_logic_vector(5 downto 0) := (others => '1');
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alias R : std_logic_vector(1 downto 0) is WHITE_PIXEL(5 downto 4);
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alias G : std_logic_vector(1 downto 0) is WHITE_PIXEL(3 downto 2);
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alias B : std_logic_vector(1 downto 0) is WHITE_PIXEL(1 downto 0);
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procedure SyncCount(signal count : inout natural;
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constant wrap : in natural;
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constant enable : in boolean;
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variable wrapped : out boolean) is
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begin
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if enable then
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if count < wrap then
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count <= count + 1;
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wrapped := false;
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else
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count <= 0;
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wrapped := true;
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end if;
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end if;
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end procedure;
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signal h_count : natural := 0;
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signal v_count : natural := 0;
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begin
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process(clk)
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variable wrapped : boolean;
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begin
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if rising_edge(clk) then
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if rst='1' then
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o_red <= (others => '0');
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o_blue <= (others => '0');
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o_green <= (others => '0');
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else
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SyncCount(h_count, H_WHOLE_LINE, true, wrapped);
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SyncCount(v_count, V_WHOLE_LINE, wrapped, wrapped);
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-- Sync Pulses
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if h_count = H_SYNC_PULSE then
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hsync <= '0';
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elsif h_count = H_BACK_PORCH then
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hsync <= '1';
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end if;
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if v_count = V_SYNC_PULSE then
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vsync <= '0';
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elsif v_count = V_BACK_PORCH then
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vsync <= '1';
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end if;
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-- To display or not to display
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if h_count < H_VISIBLE_AREA and v_count < V_VISIBLE_AREA then
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o_red <= R;
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o_green <= G;
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o_blue <= B;
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else
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o_red <= (others => '0');
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o_green <= (others => '0');
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o_blue <= (others =>'0');
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end if;
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end if;
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end if;
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end process;
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end architecture RTL;

‎test/vga_tb.vhd‎

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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity vga_tb is
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end entity vga_tb;
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architecture rtl of vga_tb is
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-- Clock
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constant CLOCK_SPEED : natural := 65e6;
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constant CLOCK_PERIOD : time := 1.0 sec / CLOCK_SPEED;
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constant DUTY_CYCLE : real := 0.5;
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signal clk : std_logic := '0';
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signal rst : std_logic := '0';
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signal hsync, vsync : std_logic;
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signal o_red, o_blue, o_green : std_logic_vector(2 downto 0);
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begin
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vga1 : entity work.vga
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port map(
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clk => clk, -- Pixel clock
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rst => rst,
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hsync => hsync,
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vsync => vsync,
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-- Input colors
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i_red => (others => '0'),
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i_blue => (others => '0'),
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i_green => (others => '0'),
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-- Output colors
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-- 8 x 8 x 8 yields 512 different colors
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o_red => o_red,
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o_blue => o_blue,
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o_green => o_green
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);
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clk <= not clk after CLOCK_PERIOD / 2;
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end architecture rtl;
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‎test/vga_tb_behav.wcfg‎

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<?xml version="1.0" encoding="UTF-8"?>
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<wave_config>
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<wave_state>
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</wave_state>
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<db_ref_list>
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<db_ref path="vga_tb_behav.wdb" id="1">
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<top_modules>
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<top_module name="vga_tb" />
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</top_modules>
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</db_ref>
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</db_ref_list>
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<zoom_setting>
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<ZoomStartTime time="0fs"></ZoomStartTime>
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<ZoomEndTime time="6111fs"></ZoomEndTime>
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<Cursor1Time time="27906906756000fs"></Cursor1Time>
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</zoom_setting>
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<column_width_setting>
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<NameColumnWidth column_width="175"></NameColumnWidth>
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<ValueColumnWidth column_width="146"></ValueColumnWidth>
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</column_width_setting>
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<WVObjectSize size="7" />
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<wvobject type="logic" fp_name="/vga_tb/clk">
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<obj_property name="ElementShortName">clk</obj_property>
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<obj_property name="ObjectShortName">clk</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/vga_tb/rst">
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<obj_property name="ElementShortName">rst</obj_property>
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<obj_property name="ObjectShortName">rst</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/vga_tb/hsync">
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<obj_property name="ElementShortName">hsync</obj_property>
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<obj_property name="ObjectShortName">hsync</obj_property>
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</wvobject>
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<wvobject type="logic" fp_name="/vga_tb/vsync">
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<obj_property name="ElementShortName">vsync</obj_property>
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<obj_property name="ObjectShortName">vsync</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/vga_tb/o_red">
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<obj_property name="ElementShortName">o_red[2:0]</obj_property>
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<obj_property name="ObjectShortName">o_red[2:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/vga_tb/o_blue">
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<obj_property name="ElementShortName">o_blue[2:0]</obj_property>
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<obj_property name="ObjectShortName">o_blue[2:0]</obj_property>
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</wvobject>
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<wvobject type="array" fp_name="/vga_tb/o_green">
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<obj_property name="ElementShortName">o_green[2:0]</obj_property>
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<obj_property name="ObjectShortName">o_green[2:0]</obj_property>
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</wvobject>
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</wave_config>

‎vga.core‎

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CAPI=2:
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name : copl:display:vga_module:0.1
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filesets:
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src:
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files:
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- src/vga.vhd : {file_type : vhdlSource-93}
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test:
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files:
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- test/vga_tb.vhd : {file_type : vhdlSource-93}
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- test/vga_tb_behav.wcfg : {file_type : user, copyto : ./}
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targets:
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sim:
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default_tool: xsim
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filesets: [src, test]
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tools:
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modelsim:
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vlog_options: [-timescale=1ns/1ns]
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xsim:
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xelab_options: [--debug, all, --timescale, 1ns/1ns]
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xsim_options: [--view, vga_tb_behav.wcfg]
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toplevel: vga_tb

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