ebi-bus-test-fpga/constraints.ucf at master · dmpro2014/ebi-bus-test-fpga · GitHub

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NET "data_in(15)" LOC = V6 | IOSTANDARD = LVCMOS33;
NET "data_in(14)" LOC = R7 | IOSTANDARD = LVCMOS33;
NET "data_in(13)" LOC = T7 | IOSTANDARD = LVCMOS33;
NET "data_in(12)" LOC = N6 | IOSTANDARD = LVCMOS33;
NET "data_in(11)" LOC = P7 | IOSTANDARD = LVCMOS33;
NET "data_in(10)" LOC = R5 | IOSTANDARD = LVCMOS33;
NET "data_in(9)" LOC = T5 | IOSTANDARD = LVCMOS33;
NET "data_in(8)" LOC = U5 | IOSTANDARD = LVCMOS33;
NET "data_in(7)" LOC = V5 | IOSTANDARD = LVCMOS33;
NET "data_in(6)" LOC = R3 | IOSTANDARD = LVCMOS33;
NET "data_in(5)" LOC = T3 | IOSTANDARD = LVCMOS33;
NET "data_in(4)" LOC = T4 | IOSTANDARD = LVCMOS33;
NET "data_in(3)" LOC = V4 | IOSTANDARD = LVCMOS33;
NET "data_in(2)" LOC = N5 | IOSTANDARD = LVCMOS33;
NET "data_in(1)" LOC = P6 | IOSTANDARD = LVCMOS33;
NET "data_in(0)" LOC = U3 | IOSTANDARD = LVCMOS33;

NET "address_in(18)" LOC = N9  | IOSTANDARD = LVCMOS33;
NET "address_in(17)" LOC = U11 | IOSTANDARD = LVCMOS33;
NET "address_in(16)" LOC = V11 | IOSTANDARD = LVCMOS33;
NET "address_in(15)" LOC = R10 | IOSTANDARD = LVCMOS33;
NET "address_in(14)" LOC = T10 | IOSTANDARD = LVCMOS33;
NET "address_in(13)" LOC = U10 | IOSTANDARD = LVCMOS33;
NET "address_in(12)" LOC = V10 | IOSTANDARD = LVCMOS33;
NET "address_in(11)" LOC = R8 | IOSTANDARD = LVCMOS33;
NET "address_in(10)" LOC = T8 | IOSTANDARD = LVCMOS33;
NET "address_in(9)" LOC = T9 | IOSTANDARD = LVCMOS33;
NET "address_in(8)" LOC = V9 | IOSTANDARD = LVCMOS33;
NET "address_in(7)" LOC = M8 | IOSTANDARD = LVCMOS33;
NET "address_in(6)" LOC = N8 | IOSTANDARD = LVCMOS33;
NET "address_in(5)" LOC = U8 | IOSTANDARD = LVCMOS33;
NET "address_in(4)" LOC = V8 | IOSTANDARD = LVCMOS33;
NET "address_in(3)" LOC = U7 | IOSTANDARD = LVCMOS33;
NET "address_in(2)" LOC = V7 | IOSTANDARD = LVCMOS33;
NET "address_in(1)" LOC = N7 | IOSTANDARD = LVCMOS33;
NET "address_in(0)" LOC = P8 | IOSTANDARD = LVCMOS33;

NET write_enable_in LOC = U13 | IOSTANDARD = LVCMOS33;
NET read_enable_in LOC = P12 | IOSTANDARD = LVCMOS33;
NET chip_select_fpga_in LOC = V13 | IOSTANDARD = LVCMOS33;
NET chip_select_sram_in LOC = M11 | IOSTANDARD = LVCMOS33;

# LEDs

NET led_1 LOC = P17 | IOSTANDARD = LVCMOS33;
NET led_2 LOC = P18 | IOSTANDARD = LVCMOS33;


#NET UART_Rx LOC=H13 | IOSTANDARD = LVCMOS33;
#NET UART_Tx LOC=H14 | IOSTANDARD = LVCMOS33;

NET clk TNM_NET = sys_clk_pin;
TIMESPEC TS_sys_clk_pin = PERIOD sys_clk_pin 40 MHz;
NET clk TNM_NET = sys_clk_pin | LOC=K15 | IOSTANDARD = LVCMOS33;

NET reset TIG;
NET reset LOC = H18 | IOSTANDARD = LVCMOS33;

CONFIG VCCAUX = "3.3";