Merge pull request #25779 from sdmaclea/arm64debug30

Pull arm/arm64 critical 5.0 PAL/diagnostic changes into 3.0

Author: sdmaclea

clrdefinitions.cmake

@@ -62,6 +62,8 @@ if (CLR_CMAKE_PLATFORM_UNIX)
   elseif (CLR_CMAKE_TARGET_ARCH_ARM)
     add_definitions(-DUNIX_ARM_ABI)
     add_definitions(-DFEATURE_DATATARGET4)
+  elseif (CLR_CMAKE_TARGET_ARCH_ARM64)
+    add_definitions(-DFEATURE_DATATARGET4)
   elseif (CLR_CMAKE_TARGET_ARCH_I386)
     add_definitions(-DUNIX_X86_ABI)
   endif()

src/debug/ee/arm64/arm64walker.cpp

@@ -200,12 +200,15 @@ BYTE*  NativeWalker::SetupOrSimulateInstructionForPatchSkip(T_CONTEXT * context,
                 switch (opc)
                 {
                 case 0: //4byte data into St
-                    RegContents = 0xFFFFFFFF & RegContents;  //zero the upper 32bit
-                    SetReg(context, RegNum, RegContents);
+                    SimdRegContents.Low = 0xFFFFFFFF & RegContents;  //zero the upper 32bit
+                    SimdRegContents.High = 0;
+                    SetSimdReg(context, RegNum, SimdRegContents);
+                    break;
                 case 1: //8byte data into Dt
-                    SetReg(context, RegNum, RegContents);
+                    SimdRegContents.Low = RegContents;
+                    SimdRegContents.High = 0;
+                    SetSimdReg(context, RegNum, SimdRegContents);
                     break;
-
                 case 2: //SIMD 16 byte data
                     SimdRegContents = GetSimdMem(ip);
                     SetSimdReg(context, RegNum, SimdRegContents);

src/pal/src/arch/arm/exceptionhelper.S

@@ -21,18 +21,27 @@ LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
 
     push_nonvol_reg {r7} /* FP. x64-RBP */
 
-    ldr	r4,	[r0, #(CONTEXT_R4)]
-    ldr	r5,	[r0, #(CONTEXT_R5)]
-    ldr	r6,	[r0, #(CONTEXT_R6)]
-    ldr	r7,	[r0, #(CONTEXT_R7)]
-    ldr	r8,	[r0, #(CONTEXT_R8)]
-    ldr	r9,	[r0, #(CONTEXT_R9)]
-    ldr	r10,	[r0, #(CONTEXT_R10)]
-    ldr	r11,	[r0, #(CONTEXT_R11)]
-    ldr	sp,	[r0, #(CONTEXT_Sp)]
-    ldr	lr,	[r0, #(CONTEXT_Pc)]
+    ldr r4,   [r0, #(CONTEXT_R4)]
+    ldr r5,   [r0, #(CONTEXT_R5)]
+    ldr r6,   [r0, #(CONTEXT_R6)]
+    ldr r7,   [r0, #(CONTEXT_R7)]
+    ldr r8,   [r0, #(CONTEXT_R8)]
+    ldr r9,   [r0, #(CONTEXT_R9)]
+    ldr r10,  [r0, #(CONTEXT_R10)]
+    ldr r11,  [r0, #(CONTEXT_R11)]
+    ldr sp,   [r0, #(CONTEXT_Sp)]
+    ldr lr,   [r0, #(CONTEXT_Pc)]
+
+    vldr d8,  [r0, #(CONTEXT_D8)]
+    vldr d9,  [r0, #(CONTEXT_D9)]
+    vldr d10, [r0, #(CONTEXT_D10)]
+    vldr d11, [r0, #(CONTEXT_D11)]
+    vldr d12, [r0, #(CONTEXT_D12)]
+    vldr d13, [r0, #(CONTEXT_D13)]
+    vldr d14, [r0, #(CONTEXT_D14)]
+    vldr d15, [r0, #(CONTEXT_D15)]
 
     // The PAL_SEHException pointer
-    mov	r0,	r1
-    b	EXTERNAL_C_FUNC(ThrowExceptionHelper)
+    mov r0, r1
+    b   EXTERNAL_C_FUNC(ThrowExceptionHelper)
 LEAF_END ThrowExceptionFromContextInternal, _TEXT

src/pal/src/arch/arm64/asmconstants.h

@@ -88,8 +88,8 @@
 #define CONTEXT_V29          CONTEXT_V28+16
 #define CONTEXT_V30          CONTEXT_V29+16
 #define CONTEXT_V31          CONTEXT_V30+16
-#define CONTEXT_FLOAT_CONTROL_OFFSET  CONTEXT_V31
+#define CONTEXT_FLOAT_CONTROL_OFFSET  CONTEXT_V31+16
 #define CONTEXT_Fpcr         0
-#define CONTEXT_Fpsr         CONTEXT_Fpcr+4
+#define CONTEXT_Fpsr         CONTEXT_Fpcr+8
 
 #endif

src/pal/src/arch/arm64/context2.S

@@ -99,9 +99,8 @@ LOCAL_LABEL(Done_CONTEXT_INTEGER):
     add x0, x0,   CONTEXT_FLOAT_CONTROL_OFFSET
     mrs x1, fpcr
     mrs x2, fpsr
-    sub x0, x0,   CONTEXT_FLOAT_CONTROL_OFFSET
     stp x1, x2,   [x0, CONTEXT_Fpcr]
-    sub x0, x0,   CONTEXT_NEON_OFFSET
+    sub x0, x0,   CONTEXT_FLOAT_CONTROL_OFFSET + CONTEXT_NEON_OFFSET
 
 LOCAL_LABEL(Done_CONTEXT_FLOATING_POINT):
     
@@ -173,10 +172,11 @@ LOCAL_LABEL(Restore_CONTEXT_FLOATING_POINT):
     ldp q26, q27, [x16, CONTEXT_V26]
     ldp q28, q29, [x16, CONTEXT_V28]
     ldp q30, q31, [x16, CONTEXT_V30]
+    add x16, x16, CONTEXT_FLOAT_CONTROL_OFFSET
     ldp x1, x2,   [x16, CONTEXT_Fpcr]
     msr fpcr, x1
     msr fpsr, x2
-    sub x16, x16,   CONTEXT_NEON_OFFSET
+    sub x16, x16,   CONTEXT_FLOAT_CONTROL_OFFSET + CONTEXT_NEON_OFFSET
 
 LOCAL_LABEL(No_Restore_CONTEXT_FLOATING_POINT):
     tbz w17, #CONTEXT_INTEGER_BIT, LOCAL_LABEL(No_Restore_CONTEXT_INTEGER)

src/pal/src/arch/arm64/exceptionhelper.S

@@ -31,6 +31,18 @@ LEAF_ENTRY ThrowExceptionFromContextInternal, _TEXT
     ldp x26,x27, [x0, #(CONTEXT_X26)]
     ldp x28,fp,  [x0, #(CONTEXT_X28)]
     ldr lr,      [x0, #(CONTEXT_Pc)]
+
+    // Restore the lower 64 bits of v8-v15
+    add x2, x0,  CONTEXT_NEON_OFFSET
+    ldr d8,      [x2, #(CONTEXT_V8 )]
+    ldr d9,      [x2, #(CONTEXT_V9 )]
+    ldr d10,     [x2, #(CONTEXT_V10)]
+    ldr d11,     [x2, #(CONTEXT_V11)]
+    ldr d12,     [x2, #(CONTEXT_V12)]
+    ldr d13,     [x2, #(CONTEXT_V13)]
+    ldr d14,     [x2, #(CONTEXT_V14)]
+    ldr d15,     [x2, #(CONTEXT_V15)]
+
     ldr x2,      [x0, #(CONTEXT_Sp)]
     mov sp, x2
 

src/pal/src/include/pal/context.h

@@ -277,6 +277,44 @@ inline void *FPREG_Xstate_Ymmh(const ucontext_t *uc)
 #define MCREG_Sp(mc)      ((mc).sp)
 #define MCREG_Pc(mc)      ((mc).pc)
 #define MCREG_Cpsr(mc)    ((mc).pstate)
+
+
+inline
+fpsimd_context* GetNativeSigSimdContext(native_context_t *mc)
+{
+    size_t size = 0;
+
+    do
+    {
+        fpsimd_context* fp = reinterpret_cast<fpsimd_context *>(&mc->uc_mcontext.__reserved[size]);
+
+        if(fp->head.magic == FPSIMD_MAGIC)
+        {
+            _ASSERTE(fp->head.size >= sizeof(fpsimd_context));
+            _ASSERTE(size + fp->head.size <= sizeof(mc->uc_mcontext.__reserved));
+
+            return fp;
+        }
+
+        if (fp->head.size == 0)
+        {
+            break;
+        }
+
+        size += fp->head.size;
+    } while (size + sizeof(fpsimd_context) <= sizeof(mc->uc_mcontext.__reserved));
+
+    _ASSERTE(false);
+
+    return nullptr;
+}
+
+inline
+const fpsimd_context* GetConstNativeSigSimdContext(const native_context_t *mc)
+{
+    return GetNativeSigSimdContext(const_cast<native_context_t*>(mc));
+}
+
 #else
     // For FreeBSD, as found in x86/ucontext.h
 #define MCREG_Rbp(mc)	    ((mc).mc_rbp)
@@ -337,6 +375,59 @@ inline void *FPREG_Xstate_Ymmh(const ucontext_t *uc)
 #define MCREG_Pc(mc)        ((mc).arm_pc)
 #define MCREG_Cpsr(mc)      ((mc).arm_cpsr)
 
+
+// Flatterned layout of the arm kernel struct vfp_sigframe
+struct VfpSigFrame
+{
+    DWORD   magic;
+    DWORD   size;
+    DWORD64 D[32]; // Some arm cpus have 16 D registers.  The kernel will ignore the extra.
+    DWORD   Fpscr;
+    DWORD   Padding;
+    DWORD   Fpexc;
+    DWORD   Fpinst;
+    DWORD   Fpinst2;
+    DWORD   Padding2;
+};
+
+inline
+VfpSigFrame* GetNativeSigSimdContext(native_context_t *mc)
+{
+    size_t size = 0;
+
+    const DWORD VfpMagic = 0x56465001; // VFP_MAGIC from arm kernel
+
+    do
+    {
+        VfpSigFrame* fp = reinterpret_cast<VfpSigFrame *>(&mc->uc_regspace[size]);
+
+        if (fp->magic == VfpMagic)
+        {
+            _ASSERTE(fp->size == sizeof(VfpSigFrame));
+            _ASSERTE(size + fp->size <= sizeof(mc->uc_regspace));
+
+            return fp;
+        }
+
+        if (fp->size == 0)
+        {
+            break;
+        }
+
+        size += fp->size;
+    } while (size + sizeof(VfpSigFrame) <= sizeof(mc->uc_regspace));
+
+    // VFP is not required on all armv7 processors, this structure may not be present
+
+    return nullptr;
+}
+
+inline
+const VfpSigFrame* GetConstNativeSigSimdContext(const native_context_t *mc)
+{
+    return GetNativeSigSimdContext(const_cast<native_context_t*>(mc));
+}
+
 #elif defined(_X86_)
 
 #define MCREG_Ebx(mc)       ((mc).mc_ebx)

src/pal/src/thread/context.cpp

@@ -465,6 +465,27 @@ void CONTEXTToNativeContext(CONST CONTEXT *lpContext, native_context_t *native)
         {
             FPREG_Xmm(native, i) = lpContext->FltSave.XmmRegisters[i];
         }
+#elif defined(_ARM64_)
+        fpsimd_context* fp = GetNativeSigSimdContext(native);
+        if (fp)
+        {
+            fp->fpsr = lpContext->Fpsr;
+            fp->fpcr = lpContext->Fpcr;
+            for (int i = 0; i < 32; i++)
+            {
+                *(NEON128*) &fp->vregs[i] = lpContext->V[i];
+            }
+        }
+#elif defined(_ARM_)
+        VfpSigFrame* fp = GetNativeSigSimdContext(native);
+        if (fp)
+        {
+            fp->Fpscr = lpContext->Fpscr;
+            for (int i = 0; i < 32; i++)
+            {
+                fp->D[i] = lpContext->D[i];
+            }
+        }
 #endif
     }
 
@@ -563,6 +584,33 @@ void CONTEXTFromNativeContext(const native_context_t *native, LPCONTEXT lpContex
         {
             lpContext->FltSave.XmmRegisters[i] = FPREG_Xmm(native, i);
         }
+#elif defined(_ARM64_)
+        const fpsimd_context* fp = GetConstNativeSigSimdContext(native);
+        if (fp)
+        {
+            lpContext->Fpsr = fp->fpsr;
+            lpContext->Fpcr = fp->fpcr;
+            for (int i = 0; i < 32; i++)
+            {
+                lpContext->V[i] = *(NEON128*) &fp->vregs[i];
+            }
+        }
+#elif defined(_ARM_)
+        const VfpSigFrame* fp = GetConstNativeSigSimdContext(native);
+        if (fp)
+        {
+            lpContext->Fpscr = fp->Fpscr;
+            for (int i = 0; i < 32; i++)
+            {
+                lpContext->D[i] = fp->D[i];
+            }
+        }
+        else
+        {
+            // Floating point state is not valid
+            // Mark the context correctly
+            lpContext->ContextFlags &= ~(ULONG)CONTEXT_FLOATING_POINT;
+        }
 #endif
     }