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Commit b9e8898

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MichalStrehovskyMichalStrehovsky
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Decouple JIT_FLAG_PREJIT from HW intrinsics (#22117)
Per dotnet/corert#6836 (comment) moving the decision whether to enable HW intrinsics to the EE side.
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‎src/jit/compiler.cpp‎

Lines changed: 69 additions & 72 deletions
Original file line numberDiff line numberDiff line change
@@ -2364,122 +2364,119 @@ void Compiler::compSetProcessor()
23642364
#ifdef _TARGET_XARCH_
23652365
opts.compSupportsISA = 0;
23662366

2367-
if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT))
2368-
{
23692367
#ifdef FEATURE_CORECLR
2370-
if (JitConfig.EnableHWIntrinsic())
2368+
if (JitConfig.EnableHWIntrinsic())
2369+
{
2370+
opts.setSupportedISA(InstructionSet_Base);
2371+
2372+
if (JitConfig.EnableSSE())
23712373
{
2372-
opts.setSupportedISA(InstructionSet_Base);
2374+
opts.setSupportedISA(InstructionSet_SSE);
2375+
#ifdef _TARGET_AMD64_
2376+
opts.setSupportedISA(InstructionSet_SSE_X64);
2377+
#endif // _TARGET_AMD64_
23732378

2374-
if (JitConfig.EnableSSE())
2379+
if (JitConfig.EnableSSE2())
23752380
{
2376-
opts.setSupportedISA(InstructionSet_SSE);
2381+
opts.setSupportedISA(InstructionSet_SSE2);
23772382
#ifdef _TARGET_AMD64_
2378-
opts.setSupportedISA(InstructionSet_SSE_X64);
2383+
opts.setSupportedISA(InstructionSet_SSE2_X64);
23792384
#endif // _TARGET_AMD64_
23802385

2381-
if (JitConfig.EnableSSE2())
2386+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AES) && JitConfig.EnableAES())
23822387
{
2383-
opts.setSupportedISA(InstructionSet_SSE2);
2384-
#ifdef _TARGET_AMD64_
2385-
opts.setSupportedISA(InstructionSet_SSE2_X64);
2386-
#endif // _TARGET_AMD64_
2388+
opts.setSupportedISA(InstructionSet_AES);
2389+
}
23872390

2388-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AES) && JitConfig.EnableAES())
2389-
{
2390-
opts.setSupportedISA(InstructionSet_AES);
2391-
}
2391+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_PCLMULQDQ) && JitConfig.EnablePCLMULQDQ())
2392+
{
2393+
opts.setSupportedISA(InstructionSet_PCLMULQDQ);
2394+
}
23922395

2393-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_PCLMULQDQ) && JitConfig.EnablePCLMULQDQ())
2394-
{
2395-
opts.setSupportedISA(InstructionSet_PCLMULQDQ);
2396-
}
2396+
// We need to additionaly check that COMPlus_EnableSSE3_4 is set, as that
2397+
// is a prexisting config flag that controls the SSE3+ ISAs
2398+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE3) && JitConfig.EnableSSE3() && JitConfig.EnableSSE3_4())
2399+
{
2400+
opts.setSupportedISA(InstructionSet_SSE3);
23972401

2398-
// We need to additionaly check that COMPlus_EnableSSE3_4 is set, as that
2399-
// is a prexisting config flag that controls the SSE3+ ISAs
2400-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE3) && JitConfig.EnableSSE3() &&
2401-
JitConfig.EnableSSE3_4())
2402+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSSE3) && JitConfig.EnableSSSE3())
24022403
{
2403-
opts.setSupportedISA(InstructionSet_SSE3);
2404+
opts.setSupportedISA(InstructionSet_SSSE3);
24042405

2405-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSSE3) && JitConfig.EnableSSSE3())
2406+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE41) && JitConfig.EnableSSE41())
24062407
{
2407-
opts.setSupportedISA(InstructionSet_SSSE3);
2408+
opts.setSupportedISA(InstructionSet_SSE41);
2409+
#ifdef _TARGET_AMD64_
2410+
opts.setSupportedISA(InstructionSet_SSE41_X64);
2411+
#endif // _TARGET_AMD64_
24082412

2409-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE41) && JitConfig.EnableSSE41())
2413+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE42) && JitConfig.EnableSSE42())
24102414
{
2411-
opts.setSupportedISA(InstructionSet_SSE41);
2415+
opts.setSupportedISA(InstructionSet_SSE42);
24122416
#ifdef _TARGET_AMD64_
2413-
opts.setSupportedISA(InstructionSet_SSE41_X64);
2417+
opts.setSupportedISA(InstructionSet_SSE42_X64);
24142418
#endif // _TARGET_AMD64_
24152419

2416-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_SSE42) && JitConfig.EnableSSE42())
2420+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_POPCNT) && JitConfig.EnablePOPCNT())
24172421
{
2418-
opts.setSupportedISA(InstructionSet_SSE42);
2422+
opts.setSupportedISA(InstructionSet_POPCNT);
24192423
#ifdef _TARGET_AMD64_
2420-
opts.setSupportedISA(InstructionSet_SSE42_X64);
2424+
opts.setSupportedISA(InstructionSet_POPCNT_X64);
24212425
#endif // _TARGET_AMD64_
2426+
}
2427+
2428+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX) && JitConfig.EnableAVX())
2429+
{
2430+
opts.setSupportedISA(InstructionSet_AVX);
24222431

2423-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_POPCNT) && JitConfig.EnablePOPCNT())
2432+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_FMA) && JitConfig.EnableFMA())
24242433
{
2425-
opts.setSupportedISA(InstructionSet_POPCNT);
2426-
#ifdef _TARGET_AMD64_
2427-
opts.setSupportedISA(InstructionSet_POPCNT_X64);
2428-
#endif // _TARGET_AMD64_
2434+
opts.setSupportedISA(InstructionSet_FMA);
24292435
}
24302436

2431-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX) && JitConfig.EnableAVX())
2437+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX2) && JitConfig.EnableAVX2())
24322438
{
2433-
opts.setSupportedISA(InstructionSet_AVX);
2434-
2435-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_FMA) && JitConfig.EnableFMA())
2436-
{
2437-
opts.setSupportedISA(InstructionSet_FMA);
2438-
}
2439-
2440-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_AVX2) && JitConfig.EnableAVX2())
2441-
{
2442-
opts.setSupportedISA(InstructionSet_AVX2);
2443-
}
2439+
opts.setSupportedISA(InstructionSet_AVX2);
24442440
}
24452441
}
24462442
}
24472443
}
24482444
}
24492445
}
24502446
}
2447+
}
24512448

2452-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_LZCNT) && JitConfig.EnableLZCNT())
2453-
{
2454-
opts.setSupportedISA(InstructionSet_LZCNT);
2449+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_LZCNT) && JitConfig.EnableLZCNT())
2450+
{
2451+
opts.setSupportedISA(InstructionSet_LZCNT);
24552452
#ifdef _TARGET_AMD64_
2456-
opts.setSupportedISA(InstructionSet_LZCNT_X64);
2453+
opts.setSupportedISA(InstructionSet_LZCNT_X64);
24572454
#endif // _TARGET_AMD64_
2458-
}
2455+
}
24592456

2460-
// We currently need to also check that AVX is supported as that controls the support for the VEX encoding
2461-
// in the emitter.
2462-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI1) && JitConfig.EnableBMI1() &&
2463-
compSupports(InstructionSet_AVX))
2464-
{
2465-
opts.setSupportedISA(InstructionSet_BMI1);
2457+
// We currently need to also check that AVX is supported as that controls the support for the VEX encoding
2458+
// in the emitter.
2459+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI1) && JitConfig.EnableBMI1() && compSupports(InstructionSet_AVX))
2460+
{
2461+
opts.setSupportedISA(InstructionSet_BMI1);
24662462
#ifdef _TARGET_AMD64_
2467-
opts.setSupportedISA(InstructionSet_BMI1_X64);
2463+
opts.setSupportedISA(InstructionSet_BMI1_X64);
24682464
#endif // _TARGET_AMD64_
2469-
}
2465+
}
24702466

2471-
// We currently need to also check that AVX is supported as that controls the support for the VEX encoding
2472-
// in the emitter.
2473-
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI2) && JitConfig.EnableBMI2() &&
2474-
compSupports(InstructionSet_AVX))
2475-
{
2476-
opts.setSupportedISA(InstructionSet_BMI2);
2467+
// We currently need to also check that AVX is supported as that controls the support for the VEX encoding
2468+
// in the emitter.
2469+
if (jitFlags.IsSet(JitFlags::JIT_FLAG_USE_BMI2) && JitConfig.EnableBMI2() && compSupports(InstructionSet_AVX))
2470+
{
2471+
opts.setSupportedISA(InstructionSet_BMI2);
24772472
#ifdef _TARGET_AMD64_
2478-
opts.setSupportedISA(InstructionSet_BMI2_X64);
2473+
opts.setSupportedISA(InstructionSet_BMI2_X64);
24792474
#endif // _TARGET_AMD64_
2480-
}
24812475
}
2476+
}
24822477
#else // !FEATURE_CORECLR
2478+
if (!jitFlags.IsSet(JitFlags::JIT_FLAG_PREJIT))
2479+
{
24832480
// If this is not FEATURE_CORECLR, the only flags supported by the VM are AVX and AVX2.
24842481
// Furthermore, the only two configurations supported by the desktop JIT are SSE2 and AVX2,
24852482
// so if the latter is set, we also check all the in-between options.
@@ -2501,8 +2498,8 @@ void Compiler::compSetProcessor()
25012498
opts.setSupportedISA(InstructionSet_AVX);
25022499
opts.setSupportedISA(InstructionSet_AVX2);
25032500
}
2504-
#endif // !FEATURE_CORECLR
25052501
}
2502+
#endif // !FEATURE_CORECLR
25062503

25072504
if (!compIsForInlining())
25082505
{

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