Implement more AVX/AVX2 intrinsics

Author: FeiPengIntel

src/jit/emitxarch.cpp

@@ -223,7 +223,12 @@ bool emitter::IsDstDstSrcAVXInstruction(instruction ins)
         case INS_unpcklpd:
         case INS_vinsertf128:
         case INS_vinserti128:
+        case INS_vmaskmovps:
+        case INS_vmaskmovpd:
         case INS_vperm2i128:
+        case INS_vperm2f128:
+        case INS_vpermilpsvar:
+        case INS_vpermilpdvar:
         case INS_vpsrlvd:
         case INS_vpsrlvq:
         case INS_vpsravd:

src/jit/hwintrinsiccodegenxarch.cpp

@@ -134,7 +134,14 @@ void CodeGen::genHWIntrinsic(GenTreeHWIntrinsic* node)
                 }
                 else if (category == HW_Category_MemoryLoad)
                 {
-                    emit->emitIns_SIMD_R_R_AR(ins, simdSize, targetReg, op1Reg, op2Reg);
+                    if (intrinsicID == NI_AVX_MaskLoad)
+                    {
+                        emit->emitIns_SIMD_R_R_AR(ins, simdSize, targetReg, op2Reg, op1Reg);
+                    }
+                    else
+                    {
+                        emit->emitIns_SIMD_R_R_AR(ins, simdSize, targetReg, op1Reg, op2Reg);
+                    }
                 }
                 else if (Compiler::isImmHWIntrinsic(intrinsicID, op2))
                 {
@@ -1331,7 +1338,6 @@ void CodeGen::genAvxOrAvx2Intrinsic(GenTreeHWIntrinsic* node)
 
             if (op1Reg != targetReg)
             {
-                instruction ins = Compiler::insOfHWIntrinsic(intrinsicID, node->gtSIMDBaseType);
                 emit->emitIns_R_R(ins, emitTypeSize(TYP_SIMD32), targetReg, op1Reg);
             }
             break;