Merge pull request #6092 from sivarv/lsrawork

Lower, LSRA and Codegen support for reg optional operands

Author: sivarv

src/jit/codegenxarch.cpp

@@ -1238,8 +1238,13 @@ void CodeGen::genCodeForDivMod(GenTreeOp* treeNode)
     genConsumeOperands(treeNode->AsOp());
     if (varTypeIsFloating(targetType))
     {
-        // divisor is not contained or if contained is a memory op
-        assert(!divisor->isContained() || divisor->isMemoryOp() || divisor->IsCnsFltOrDbl());
+        // divisor is not contained or if contained is a memory op.
+        // Note that a reg optional operand is a treated as a memory op
+        // if no register is allocated to it.
+        assert(!divisor->isContained() || 
+               divisor->isMemoryOp() || 
+               divisor->IsCnsFltOrDbl() ||
+               divisor->IsRegOptional());
 
         // Floating point div/rem operation
         assert(oper == GT_DIV || oper == GT_MOD);
@@ -1357,7 +1362,10 @@ void CodeGen::genCodeForBinary(GenTree* treeNode)
     if (op1->isContained())
     {
         assert(treeNode->OperIsCommutative());
-        assert(op1->isMemoryOp() || op1->IsCnsNonZeroFltOrDbl() || op1->IsIntCnsFitsInI32());
+        assert(op1->isMemoryOp() || 
+               op1->IsCnsNonZeroFltOrDbl() || 
+               op1->IsIntCnsFitsInI32() ||
+               op1->IsRegOptional());
 
         op1 = treeNode->gtGetOp2();
         op2 = treeNode->gtGetOp1();
@@ -2203,8 +2211,8 @@ CodeGen::genCodeForTreeNode(GenTreePtr treeNode)
             bool isUnsignedMultiply    = ((treeNode->gtFlags & GTF_UNSIGNED) != 0);
             bool requiresOverflowCheck = treeNode->gtOverflowEx();
 
-            GenTree *op1 = treeNode->gtOp.gtOp1;
-            GenTree *op2 = treeNode->gtOp.gtOp2;
+            GenTree* op1 = treeNode->gtGetOp1();
+            GenTree* op2 = treeNode->gtGetOp2();
 
             // there are 3 forms of x64 multiply:
             // 1-op form with 128 result:  RDX:RAX = RAX * rm
@@ -4958,6 +4966,18 @@ void CodeGen::genConsumeRegs(GenTree* tree)
             // Now we need to consume the operands of the GT_AND node.
             genConsumeOperands(tree->AsOp());
         }
+        else if (tree->OperGet() == GT_LCL_VAR)
+        {
+            // A contained lcl var must be living on stack and marked as reg optional.
+            unsigned varNum = tree->AsLclVarCommon()->GetLclNum();
+            LclVarDsc* varDsc = compiler->lvaTable + varNum;
+
+            noway_assert(varDsc->lvRegNum == REG_STK);
+            noway_assert(tree->IsRegOptional());
+
+            // Update the life of reg optional lcl var.
+            genUpdateLife(tree);
+        }
         else
         {
             assert(tree->OperIsLeaf());
@@ -5488,10 +5508,15 @@ void CodeGen::genStoreInd(GenTreePtr node)
                     rmwDst = data->gtGetOp2();
                     rmwSrc = data->gtGetOp1();
                 }
+
+                genConsumeRegs(rmwSrc);
             }
             else
             {
-                // For unary RMW ops, src and dst of RMW memory op is the same.
+                // *(p) = oper *(p): Here addr = p, rmwsrc=rmwDst = *(p) i.e. GT_IND(p)
+                // For unary RMW ops, src and dst of RMW memory op is the same.  Lower
+                // clears operand counts on rmwSrc and we don't need to perform a
+                // genConsumeReg() on it.
                 assert(storeInd->IsRMWDstOp1());
                 rmwSrc = data->gtGetOp1();
                 rmwDst = data->gtGetOp1();
@@ -5500,9 +5525,7 @@ void CodeGen::genStoreInd(GenTreePtr node)
 
             assert(rmwSrc != nullptr);
             assert(rmwDst != nullptr);
-            assert(Lowering::IndirsAreEquivalent(rmwDst, storeInd));
-
-            genConsumeRegs(rmwSrc);
+            assert(Lowering::IndirsAreEquivalent(rmwDst, storeInd));             
         }
         else
         {

src/jit/emitxarch.cpp

@@ -2845,17 +2845,22 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
 {
     // dst can only be a reg or modrm
     assert(!dst->isContained() ||
-           dst->isContainedIndir() ||
-           dst->isContainedLclField() ||
+           dst->isContainedMemoryOp() ||
            instrIs3opImul(ins)); // dst on these isn't really the dst
 
+#ifdef DEBUG
     // src can be anything but both src and dst cannot be addr modes
     // or at least cannot be contained addr modes
-    if (dst->isContainedIndir())
-        assert(!src->isContainedIndir());
+    if (dst->isContainedMemoryOp())
+    {
+        assert(!src->isContainedMemoryOp());
+    }
 
-    if (src->isContainedLclField())
-        assert(!dst->isContained());
+    if (src->isContainedMemoryOp())
+    {
+        assert(!dst->isContainedMemoryOp());
+    }
+#endif
 
     // find which operand is a memory op (if any)
     // and what its base is
@@ -2890,7 +2895,7 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
     }
 
     // find local field if any
-    GenTreeLclFld* lclField = nullptr;
+    GenTreeLclFld* lclField = nullptr;    
     if (src->isContainedLclField())
     {
         lclField = src->AsLclFld();
@@ -2900,9 +2905,22 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
         lclField = dst->AsLclFld();
     }
 
+    // find contained lcl var if any
+    GenTreeLclVar* lclVar = nullptr;
+    if (src->isContainedLclVar())
+    {
+        assert(src->IsRegOptional());
+        lclVar = src->AsLclVar();
+    }
+    else if (dst->isContainedLclVar())
+    {
+        assert(dst->IsRegOptional());
+        lclVar = dst->AsLclVar();
+    }
+
     // First handle the simple non-memory cases
     //
-    if ((mem == nullptr) && (lclField == nullptr))
+    if ((mem == nullptr) && (lclField == nullptr) && (lclVar == nullptr))
     {
         if (intConst != nullptr)
         {
@@ -2938,15 +2956,27 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
         return dst->gtRegNum;
     }
 
-    // Next handle the cases where we have a stack based local memory operand
+    // Next handle the cases where we have a stack based local memory operand.
     //
-    if (lclField)
+    unsigned varNum = BAD_VAR_NUM;
+    unsigned offset = (unsigned) -1;
+
+    if (lclField != nullptr)
     {
-        unsigned offset = lclField->gtLclFld.gtLclOffs;
-        unsigned varNum = lclField->gtLclVarCommon.gtLclNum;
+        varNum = lclField->AsLclVarCommon()->GetLclNum();
+        offset = lclField->gtLclFld.gtLclOffs;
+    }
+    else if (lclVar != nullptr)
+    {
+        varNum = lclVar->AsLclVarCommon()->GetLclNum();
+        offset = 0;
+    }
 
+    if (varNum != BAD_VAR_NUM)
+    {
         // Is the memory op in the source position?
-        if (src->isContainedLclField())
+        if (src->isContainedLclField() ||
+            src->isContainedLclVar())
         {
             if (instrHasImplicitRegPairDest(ins))
             {
@@ -2964,6 +2994,7 @@ regNumber emitter::emitInsBinary(instruction ins, emitAttr attr, GenTree* dst, G
         else  // The memory op is in the dest position.
         {
             assert(dst->gtRegNum == REG_NA);
+
             // src could be int or reg
             if (src->isContainedIntOrIImmed())
             {

src/jit/gentree.cpp

@@ -12869,6 +12869,19 @@ BasicBlock* BasicBlock::GetSucc(unsigned i, Compiler * comp)
     }
 }
 
+// -------------------------------------------------------------------------
+// IsRegOptional: Returns true if this gentree node is marked by lowering to
+// indicate that codegen can still generate code even if it wasn't allocated
+// a register.
+bool GenTree::IsRegOptional() const
+{
+#ifdef LEGACY_BACKEND
+    return false;
+#else
+    return gtLsraInfo.regOptional;
+#endif
+}
+
 bool GenTree::IsPhiDefn()
 {
     bool res = 

src/jit/gentree.h

@@ -495,11 +495,16 @@ struct GenTree
 
     bool isContainedLclField() const        { return isContained() && isLclField(); }
 
+    bool isContainedLclVar() const          {  return isContained() && (OperGet() == GT_LCL_VAR);  } 
+
     // Indicates whether it is a memory op.
     // Right now it includes Indir and LclField ops.
     bool isMemoryOp() const                 { return isIndir() || isLclField(); }
 
-    bool isContainedMemoryOp() const        { return isContained() && isMemoryOp(); }
+    bool isContainedMemoryOp() const        
+    { 
+        return (isContained() && isMemoryOp()) || isContainedLclVar(); 
+    }
 
     regNumber GetRegNum() const
     {
@@ -1620,6 +1625,11 @@ struct GenTree
     inline var_types            CastFromType();
     inline var_types&           CastToType();
 
+    // Returns true if this gentree node is marked by lowering to indicate
+    // that codegen can still generate code even if it wasn't allocated a 
+    // register.
+    bool IsRegOptional() const;   
+
     // Returns "true" iff "*this" is an assignment (GT_ASG) tree that defines an SSA name (lcl = phi(...));
     bool IsPhiDefn();
 

src/jit/lower.h

@@ -145,6 +145,8 @@ class Lowering : public Phase
     void TreeNodeInfoInit(GenTreePtr* tree, GenTree* parent);
 #if defined(_TARGET_XARCH_)
     void TreeNodeInfoInitSimple(GenTree* tree);
+    void SetRegOptionalForBinOp(GenTree* tree);
+    void TryToSetRegOptional(GenTree* operand);
 #endif // defined(_TARGET_XARCH_)
     void TreeNodeInfoInitReturn(GenTree* tree);
     void TreeNodeInfoInitShiftRotate(GenTree* tree);