@@ -9255,15 +9255,15 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
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case NI_AVX_LoadAlignedVector256:
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case NI_AVX512_LoadAlignedVector512:
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{
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- // In minOpts , we need to ensure that an unaligned address will fault when an explicit LoadAligned is used.
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- // Non-VEX encoded instructions will fault if an unaligned SIMD16 load is contained but will not for scalar
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- // loads, and VEX-encoded instructions will not fault for unaligned loads in any case.
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+ // For debug code , we need to ensure that an unaligned address will fault when an explicit LoadAligned is
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+ // used. Non-VEX encoded instructions will fault if an unaligned SIMD16 load is contained but will not for
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+ // scalar loads, and VEX-encoded instructions will not fault for unaligned loads in any case.
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//
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// When optimizations are enabled, we want to contain any aligned load that is large enough for the parent's
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// requirement.
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- return (supportsSIMDLoad &&
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- (( !comp->canUseVexEncoding () && expectedSize == genTypeSize (TYP_SIMD16)) || !comp-> opts . MinOpts ( )));
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+ return (supportsSIMDLoad && (comp-> opts . OptimizationEnabled () ||
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+ ( !comp->canUseVexEncoding () && expectedSize == genTypeSize (TYP_SIMD16))));
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}
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case NI_X86Base_LoadScalarVector128:
@@ -9279,7 +9279,7 @@ bool Lowering::IsContainableHWIntrinsicOp(GenTreeHWIntrinsic* parentNode, GenTre
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case NI_AVX2_BroadcastScalarToVector256:
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case NI_AVX512_BroadcastScalarToVector512:
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{
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- if (comp->opts .MinOpts () || !comp->canUseEmbeddedBroadcast ())
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+ if (! comp->opts .Tier0OptimizationEnabled () || !comp->canUseEmbeddedBroadcast ())
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{
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return false ;
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}
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