@@ -18444,7 +18444,10 @@ unsigned GenTreeVecCon::ElementCount(unsigned simdSize, var_types simdBaseType)
1844418444 return simdSize / genTypeSize(simdBaseType);
1844518445}
1844618446
18447- bool Compiler::IsValidForShuffle(GenTree* indices, unsigned simdSize, var_types simdBaseType, bool* canBecomeValid) const
18447+ bool Compiler::IsValidForShuffle(GenTree* indices,
18448+ unsigned simdSize,
18449+ var_types simdBaseType,
18450+ bool* canBecomeValid) const
1844818451{
1844918452#if defined(TARGET_XARCH)
1845018453 if (canBecomeValid)
@@ -25514,14 +25517,14 @@ GenTree* Compiler::gtNewSimdShuffleNodeVariable(
2551425517 else if (elementSize == 8 && simdSize == 16 && compOpportunisticallyDependsOn(InstructionSet_AVX512F_VL))
2551525518 {
2551625519 GenTree* op1Copy = fgMakeMultiUse(&op1); // just use op1 again for the other variable
25517- retNode
25518- = gtNewSimdHWIntrinsicNode(type, op1, op2, op1Copy, NI_AVX512F_VL_PermuteVar2x64x2, simdBaseJitType,
25519- simdSize);
25520+ retNode = gtNewSimdHWIntrinsicNode(type, op1, op2, op1Copy, NI_AVX512F_VL_PermuteVar2x64x2, simdBaseJitType,
25521+ simdSize);
2552025522 }
2552125523 else if (elementSize == 8 && simdSize == 16 && compOpportunisticallyDependsOn(InstructionSet_AVX10v1))
2552225524 {
2552325525 GenTree* op1Copy = fgMakeMultiUse(&op1); // just use op1 again for the other variable
25524- retNode = gtNewSimdHWIntrinsicNode(type, op1, op2, op1Copy, NI_AVX10v1_PermuteVar2x64x2, simdBaseJitType, simdSize);
25526+ retNode =
25527+ gtNewSimdHWIntrinsicNode(type, op1, op2, op1Copy, NI_AVX10v1_PermuteVar2x64x2, simdBaseJitType, simdSize);
2552525528 }
2552625529 else
2552725530 {
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