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jacob-crawleyjacob-crawley
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SVE2 FP APIs (#118332)
Contributing towards [#115479](#115479) Contains implementations for the set of [SVE2 FP APIs](#94018 (comment)), aside from `ConvertToSingleOdd` and `ConvertToSingleOddRoundToOdd`. This is due to concerns I have about the API proposal for these intrinsics being incorrect, when I have a resolution to [my comments](#94018 (comment)) on this they will be implemented.
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15 files changed

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‎src/coreclr/jit/codegenarm64test.cpp‎

Lines changed: 32 additions & 32 deletions
Original file line numberDiff line numberDiff line change
@@ -6977,19 +6977,19 @@ void CodeGen::genArm64EmitterUnitTestsSve()
69776977
// IF_SVE_EK_3A
69786978
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V0, REG_V1, REG_V2, 0,
69796979
INS_OPTS_SCALABLE_B); // CMLA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6980-
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V3, REG_V4, REG_V5, 90,
6980+
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V3, REG_V4, REG_V5, 1,
69816981
INS_OPTS_SCALABLE_H); // CMLA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6982-
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V7, REG_V8, 180,
6982+
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V7, REG_V8, 2,
69836983
INS_OPTS_SCALABLE_S); // CMLA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6984-
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V9, REG_V10, REG_V11, 270,
6984+
theEmitter->emitIns_R_R_R_I(INS_sve_cmla, EA_SCALABLE, REG_V9, REG_V10, REG_V11, 3,
69856985
INS_OPTS_SCALABLE_D); // CMLA <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
69866986
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V12, REG_V13, REG_V14, 0,
69876987
INS_OPTS_SCALABLE_B); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6988-
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V15, REG_V16, REG_V17, 90,
6988+
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V15, REG_V16, REG_V17, 1,
69896989
INS_OPTS_SCALABLE_H); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6990-
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V18, REG_V19, REG_V20, 180,
6990+
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V18, REG_V19, REG_V20, 2,
69916991
INS_OPTS_SCALABLE_S); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
6992-
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V21, REG_V22, REG_V23, 270,
6992+
theEmitter->emitIns_R_R_R_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V21, REG_V22, REG_V23, 3,
69936993
INS_OPTS_SCALABLE_D); // SQRDCMLAH <Zda>.<T>, <Zn>.<T>, <Zm>.<T>, <const>
69946994

69956995
#ifdef ALL_ARM64_EMITTER_UNIT_TESTS_SVE_UNSUPPORTED
@@ -7289,21 +7289,21 @@ void CodeGen::genArm64EmitterUnitTestsSve()
72897289
INS_OPTS_SCALABLE_D); // USHLLT <Zd>.<T>, <Zn>.<Tb>, #<const>
72907290

72917291
// IF_SVE_FV_2A
7292-
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V0, REG_V1, 90,
7292+
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V0, REG_V1, 0,
72937293
INS_OPTS_SCALABLE_B); // CADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7294-
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V2, REG_V3, 90,
7294+
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V2, REG_V3, 0,
72957295
INS_OPTS_SCALABLE_H); // CADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7296-
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V4, REG_V5, 270,
7296+
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V4, REG_V5, 1,
72977297
INS_OPTS_SCALABLE_S); // CADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7298-
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V6, REG_V7, 270,
7298+
theEmitter->emitIns_R_R_I(INS_sve_cadd, EA_SCALABLE, REG_V6, REG_V7, 1,
72997299
INS_OPTS_SCALABLE_D); // CADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7300-
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V8, REG_V9, 270,
7300+
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V8, REG_V9, 1,
73017301
INS_OPTS_SCALABLE_B); // SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7302-
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V10, REG_V11, 270,
7302+
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V10, REG_V11, 1,
73037303
INS_OPTS_SCALABLE_H); // SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7304-
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V12, REG_V13, 90,
7304+
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V12, REG_V13, 0,
73057305
INS_OPTS_SCALABLE_S); // SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
7306-
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V14, REG_V15, 90,
7306+
theEmitter->emitIns_R_R_I(INS_sve_sqcadd, EA_SCALABLE, REG_V14, REG_V15, 0,
73077307
INS_OPTS_SCALABLE_D); // SQCADD <Zdn>.<T>, <Zdn>.<T>, <Zm>.<T>, <const>
73087308

73097309
// IF_SVE_FY_3A
@@ -7365,61 +7365,61 @@ void CodeGen::genArm64EmitterUnitTestsSve()
73657365
// IF_SVE_FA_3A
73667366
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V0, REG_V7, REG_V1, 3, 0,
73677367
INS_OPTS_SCALABLE_B); // CDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
7368-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 90,
7368+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 1,
73697369
INS_OPTS_SCALABLE_B); // CDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
7370-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 180,
7370+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 2,
73717371
INS_OPTS_SCALABLE_B); // CDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
7372-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 270,
7372+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 3,
73737373
INS_OPTS_SCALABLE_B); // CDOT <Zda>.S, <Zn>.B, <Zm>.B[<imm>], <const>
73747374

73757375
// IF_SVE_FA_3B
73767376
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V0, REG_V1, REG_V0, 0, 0,
73777377
INS_OPTS_SCALABLE_H); // CDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
7378-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 90,
7378+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 1,
73797379
INS_OPTS_SCALABLE_H); // CDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
7380-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 180,
7380+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 2,
73817381
INS_OPTS_SCALABLE_H); // CDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
7382-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 270,
7382+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cdot, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 3,
73837383
INS_OPTS_SCALABLE_H); // CDOT <Zda>.D, <Zn>.H, <Zm>.H[<imm>], <const>
73847384

73857385
// IF_SVE_FB_3A
73867386
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V0, REG_V7, REG_V1, 3, 0,
73877387
INS_OPTS_SCALABLE_H); // CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7388-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 90,
7388+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 1,
73897389
INS_OPTS_SCALABLE_H); // CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7390-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 180,
7390+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 2,
73917391
INS_OPTS_SCALABLE_H); // CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7392-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 270,
7392+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 3,
73937393
INS_OPTS_SCALABLE_H); // CMLA <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
73947394

73957395
// IF_SVE_FB_3B
73967396
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V0, REG_V1, REG_V0, 0, 0,
73977397
INS_OPTS_SCALABLE_S); // CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7398-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 90,
7398+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 1,
73997399
INS_OPTS_SCALABLE_S); // CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7400-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 180,
7400+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 2,
74017401
INS_OPTS_SCALABLE_S); // CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7402-
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 270,
7402+
theEmitter->emitIns_R_R_R_I_I(INS_sve_cmla, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 3,
74037403
INS_OPTS_SCALABLE_S); // CMLA <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
74047404

74057405
// IF_SVE_FC_3A
74067406
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V0, REG_V7, REG_V1, 3, 0,
74077407
INS_OPTS_SCALABLE_H); // SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7408-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 90,
7408+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V2, REG_V5, REG_V3, 2, 1,
74097409
INS_OPTS_SCALABLE_H); // SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7410-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 180,
7410+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V4, REG_V3, REG_V5, 1, 2,
74117411
INS_OPTS_SCALABLE_H); // SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
7412-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 270,
7412+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V6, REG_V1, REG_V7, 0, 3,
74137413
INS_OPTS_SCALABLE_H); // SQRDCMLAH <Zda>.H, <Zn>.H, <Zm>.H[<imm>], <const>
74147414

74157415
// IF_SVE_FC_3B
74167416
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V0, REG_V1, REG_V0, 0, 0,
74177417
INS_OPTS_SCALABLE_S); // SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7418-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 90,
7418+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V2, REG_V3, REG_V5, 1, 1,
74197419
INS_OPTS_SCALABLE_S); // SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7420-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 180,
7420+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V4, REG_V5, REG_V10, 0, 2,
74217421
INS_OPTS_SCALABLE_S); // SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
7422-
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 270,
7422+
theEmitter->emitIns_R_R_R_I_I(INS_sve_sqrdcmlah, EA_SCALABLE, REG_V6, REG_V7, REG_V15, 1, 3,
74237423
INS_OPTS_SCALABLE_S); // SQRDCMLAH <Zda>.S, <Zn>.S, <Zm>.S[<imm>], <const>
74247424

74257425
// IF_SVE_IH_3A

‎src/coreclr/jit/emitarm64sve.cpp‎

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -2645,9 +2645,9 @@ void emitter::emitInsSve_R_R_I(instruction ins,
26452645
assert(isVectorRegister(reg1)); // ddddd
26462646
assert(isVectorRegister(reg2)); // nnnnn
26472647
assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx
2648+
assert(isValidRot(emitDecodeRotationImm90_or_270(imm)));
26482649

26492650
// Convert rot to bitwise representation: 0 if 90, 1 if 270
2650-
imm = emitEncodeRotationImm90_or_270(imm); // r
26512651
fmt = IF_SVE_FV_2A;
26522652
break;
26532653

@@ -4574,14 +4574,13 @@ void emitter::emitInsSve_R_R_R_I(instruction ins,
45744574
case INS_sve_sqrdcmlah:
45754575
assert(insScalableOptsNone(sopt));
45764576
assert(insOptsScalableStandard(opt));
4577-
assert(isVectorRegister(reg1)); // ddddd
4578-
assert(isVectorRegister(reg2)); // nnnnn
4579-
assert(isVectorRegister(reg3)); // mmmmm
4580-
assert(isValidRot(imm)); // rr
4581-
assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx
4577+
assert(isVectorRegister(reg1)); // ddddd
4578+
assert(isVectorRegister(reg2)); // nnnnn
4579+
assert(isVectorRegister(reg3)); // mmmmm
4580+
assert(isValidRot(emitDecodeRotationImm0_to_270(imm))); // rr
4581+
assert(isValidVectorElemsize(optGetSveElemsize(opt))); // xx
45824582

45834583
// Convert rot to bitwise representation
4584-
imm = emitEncodeRotationImm0_to_270(imm);
45854584
fmt = IF_SVE_EK_3A;
45864585
break;
45874586

@@ -5785,12 +5784,12 @@ void emitter::emitInsSve_R_R_R_I_I(instruction ins,
57855784
break;
57865785

57875786
case INS_sve_cmla:
5788-
assert(isVectorRegister(reg1)); // ddddd
5789-
assert(isVectorRegister(reg2)); // nnnnn
5790-
assert(isLowVectorRegister(reg3)); // mmmm
5791-
assert(isValidRot(imm2)); // rr
5787+
assert(isVectorRegister(reg1)); // ddddd
5788+
assert(isVectorRegister(reg2)); // nnnnn
5789+
assert(isLowVectorRegister(reg3)); // mmmm
5790+
assert(isValidRot(emitDecodeRotationImm0_to_270(imm2))); // rr
57925791
// Convert imm2 from rotation value (0-270) to bitwise representation (0-3)
5793-
imm = (imm1 << 2) | emitEncodeRotationImm0_to_270(imm2);
5792+
imm = (imm1 << 2) | imm2;
57945793

57955794
if (opt == INS_OPTS_SCALABLE_H)
57965795
{
@@ -5807,13 +5806,12 @@ void emitter::emitInsSve_R_R_R_I_I(instruction ins,
58075806
break;
58085807

58095808
case INS_sve_sqrdcmlah:
5810-
assert(isVectorRegister(reg1)); // ddddd
5811-
assert(isVectorRegister(reg2)); // nnnnn
5812-
assert(isLowVectorRegister(reg3)); // mmmm
5813-
assert(isValidRot(imm2)); // rr
5814-
// Convert imm2 from rotation value (0-270) to bitwise representation (0-3)
5815-
imm = (imm1 << 2) | emitEncodeRotationImm0_to_270(imm2);
5809+
assert(isVectorRegister(reg1)); // ddddd
5810+
assert(isVectorRegister(reg2)); // nnnnn
5811+
assert(isLowVectorRegister(reg3)); // mmmm
5812+
assert(isValidRot(emitDecodeRotationImm0_to_270(imm2))); // rr
58165813

5814+
imm = (imm1 << 2) | imm2;
58175815
if (opt == INS_OPTS_SCALABLE_H)
58185816
{
58195817
assert(isValidUimm<2>(imm1)); // ii

‎src/coreclr/jit/hwintrinsic.h‎

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1275,6 +1275,8 @@ struct HWIntrinsicInfo
12751275
}
12761276

12771277
case NI_Sve_MultiplyAddRotateComplexBySelectedScalar:
1278+
case NI_Sve2_MultiplyAddRotateComplexBySelectedScalar:
1279+
case NI_Sve2_MultiplyAddRoundedDoublingSaturateHighRotateComplexBySelectedScalar:
12781280
case NI_Sve2_DotProductRotateComplexBySelectedIndex:
12791281
{
12801282
assert(sig->numArgs == 5);

‎src/coreclr/jit/hwintrinsicarm64.cpp‎

Lines changed: 41 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -445,11 +445,15 @@ void HWIntrinsicInfo::lookupImmBounds(
445445
break;
446446

447447
case NI_Sve_AddRotateComplex:
448+
case NI_Sve2_AddRotateComplex:
449+
case NI_Sve2_AddSaturateRotateComplex:
448450
immLowerBound = 0;
449451
immUpperBound = 1;
450452
break;
451453

452454
case NI_Sve_MultiplyAddRotateComplex:
455+
case NI_Sve2_MultiplyAddRotateComplex:
456+
case NI_Sve2_MultiplyAddRoundedDoublingSaturateHighRotateComplex:
453457
case NI_Sve2_DotProductRotateComplex:
454458
immLowerBound = 0;
455459
immUpperBound = 3;
@@ -493,6 +497,41 @@ void HWIntrinsicInfo::lookupImmBounds(
493497
}
494498
break;
495499

500+
case NI_Sve2_MultiplyAddRotateComplexBySelectedScalar:
501+
if (immNumber == 1)
502+
{
503+
// Bounds for rotation
504+
immLowerBound = 0;
505+
immUpperBound = 3;
506+
}
507+
else
508+
{
509+
// Bounds for index
510+
assert(immNumber == 2);
511+
assert(baseType == TYP_USHORT || baseType == TYP_SHORT || baseType == TYP_INT ||
512+
baseType == TYP_UINT);
513+
immLowerBound = 0;
514+
immUpperBound = (baseType == TYP_USHORT || baseType == TYP_SHORT) ? 3 : 1;
515+
}
516+
break;
517+
518+
case NI_Sve2_MultiplyAddRoundedDoublingSaturateHighRotateComplexBySelectedScalar:
519+
if (immNumber == 1)
520+
{
521+
// Bounds for rotation
522+
immLowerBound = 0;
523+
immUpperBound = 3;
524+
}
525+
else
526+
{
527+
// Bounds for index
528+
assert(immNumber == 2);
529+
assert(baseType == TYP_INT || baseType == TYP_SHORT);
530+
immLowerBound = 0;
531+
immUpperBound = (baseType == TYP_SHORT) ? 3 : 1;
532+
}
533+
break;
534+
496535
case NI_Sve_TrigonometricMultiplyAddCoefficient:
497536
immLowerBound = 0;
498537
immUpperBound = 7;
@@ -3180,6 +3219,8 @@ GenTree* Compiler::impSpecialIntrinsic(NamedIntrinsic intrinsic,
31803219
}
31813220

31823221
case NI_Sve_MultiplyAddRotateComplexBySelectedScalar:
3222+
case NI_Sve2_MultiplyAddRotateComplexBySelectedScalar:
3223+
case NI_Sve2_MultiplyAddRoundedDoublingSaturateHighRotateComplexBySelectedScalar:
31833224
case NI_Sve2_DotProductRotateComplexBySelectedIndex:
31843225
{
31853226
assert(sig->numArgs == 5);

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