[AArch64] arm64-bitfield-extract.ll - regenerate test checks

Author: RKSimon

llvm/test/CodeGen/AArch64/arm64-bitfield-extract.ll

@@ -1,5 +1,5 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
-; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
+; RUN: opt -passes="require<profile-summary>,function(codegenprepare)" -mtriple=arm64-apple=ios -S -o - %s | FileCheck --check-prefix=OPT %s
 ; RUN: llc < %s -mtriple=arm64-eabi | FileCheck --check-prefix=LLC %s
 
 %struct.X = type { i8, i8, [2 x i8] }
@@ -618,7 +618,7 @@ define void @fct16(ptr nocapture %y, i32 %x) nounwind optsize inlinehint ssp {
 ; LLC-LABEL: fct16:
 ; LLC:       // %bb.0: // %entry
 ; LLC-NEXT:    ldr w8, [x0]
-; LLC-NEXT:    mov w9, #33120
+; LLC-NEXT:    mov w9, #33120 // =0x8160
 ; LLC-NEXT:    movk w9, #26, lsl #16
 ; LLC-NEXT:    and w8, w8, w9
 ; LLC-NEXT:    bfxil w8, w1, #16, #3
@@ -655,7 +655,7 @@ define void @fct16_mask(ptr nocapture %y, i32 %x) nounwind optsize inlinehint ss
 ; LLC-LABEL: fct16_mask:
 ; LLC:       // %bb.0: // %entry
 ; LLC-NEXT:    ldr w8, [x0]
-; LLC-NEXT:    mov w9, #33120
+; LLC-NEXT:    mov w9, #33120 // =0x8160
 ; LLC-NEXT:    movk w9, #26, lsl #16
 ; LLC-NEXT:    and w8, w8, w9
 ; LLC-NEXT:    bfxil w8, w1, #16, #3
@@ -697,7 +697,7 @@ define void @fct17(ptr nocapture %y, i64 %x) nounwind optsize inlinehint ssp {
 ; LLC-LABEL: fct17:
 ; LLC:       // %bb.0: // %entry
 ; LLC-NEXT:    ldr x8, [x0]
-; LLC-NEXT:    mov w9, #33120
+; LLC-NEXT:    mov w9, #33120 // =0x8160
 ; LLC-NEXT:    movk w9, #26, lsl #16
 ; LLC-NEXT:    and x8, x8, x9
 ; LLC-NEXT:    bfxil x8, x1, #16, #3
@@ -734,7 +734,7 @@ define void @fct17_mask(ptr nocapture %y, i64 %x) nounwind optsize inlinehint ss
 ; LLC-LABEL: fct17_mask:
 ; LLC:       // %bb.0: // %entry
 ; LLC-NEXT:    ldr x8, [x0]
-; LLC-NEXT:    mov w9, #33120
+; LLC-NEXT:    mov w9, #33120 // =0x8160
 ; LLC-NEXT:    movk w9, #26, lsl #16
 ; LLC-NEXT:    and x8, x8, x9
 ; LLC-NEXT:    bfxil x8, x1, #16, #3
@@ -819,7 +819,7 @@ define i32 @fct19(i64 %arg1) nounwind readonly ssp  {
 ; LLC-NEXT:    add w0, w8, #32
 ; LLC-NEXT:    ret
 ; LLC-NEXT:  .LBB26_6:
-; LLC-NEXT:    mov w0, #64
+; LLC-NEXT:    mov w0, #64 // =0x40
 ; LLC-NEXT:    ret
 ; OPT-LABEL: @fct19(
 ; OPT-NEXT:  entry:
@@ -916,20 +916,20 @@ return:                                           ; preds = %if.end13, %if.then1
 define i80 @fct20(i128 %a, i128 %b) {
 ; LLC-LABEL: fct20:
 ; LLC:       // %bb.0: // %entry
-; LLC-NEXT:	mov	x12, #11776                     // =0x2e00
-; LLC-NEXT:	lsr	x8, x1, #18
-; LLC-NEXT:	extr	x9, x1, x0, #18
-; LLC-NEXT:	movk	x12, #25856, lsl #16
-; LLC-NEXT:	orr	x10, x2, x3
-; LLC-NEXT:	mov	w11, #26220                     // =0x666c
-; LLC-NEXT:	movk	x12, #11077, lsl #32
-; LLC-NEXT:	and	x11, x8, x11
-; LLC-NEXT:	cmp	x10, #0
-; LLC-NEXT:	movk	x12, #45, lsl #48
-; LLC-NEXT:	csel	x1, x11, x8, eq
-; LLC-NEXT:	and	x12, x9, x12
-; LLC-NEXT:	csel	x0, x12, x9, eq
-; LLC-NEXT:	ret
+; LLC-NEXT:    mov x12, #11776 // =0x2e00
+; LLC-NEXT:    lsr x8, x1, #18
+; LLC-NEXT:    extr x9, x1, x0, #18
+; LLC-NEXT:    movk x12, #25856, lsl #16
+; LLC-NEXT:    orr x10, x2, x3
+; LLC-NEXT:    mov w11, #26220 // =0x666c
+; LLC-NEXT:    movk x12, #11077, lsl #32
+; LLC-NEXT:    and x11, x8, x11
+; LLC-NEXT:    cmp x10, #0
+; LLC-NEXT:    movk x12, #45, lsl #48
+; LLC-NEXT:    csel x1, x11, x8, eq
+; LLC-NEXT:    and x12, x9, x12
+; LLC-NEXT:    csel x0, x12, x9, eq
+; LLC-NEXT:    ret
 ; OPT-LABEL: @fct20(
 ; OPT-NEXT:  entry:
 ; OPT-NEXT:    [[SHR:%.*]] = lshr i128 [[A:%.*]], 18