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2023 clean-up and update
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‎.github/workflows/ci.yaml‎

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name: Async_FIFO
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on: [push]
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jobs:
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Lint:
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runs-on: macos-latest
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steps:
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- uses: actions/checkout@v2
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- run: brew install verilator
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- run: ./flow.sh lint
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Simulation:
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runs-on: macos-latest
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steps:
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- uses: actions/checkout@v2
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- run: brew install verilator
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- run: brew install icarus-verilog
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- run: ./flow.sh sim
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Synthesis:
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runs-on: macos-latest
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steps:
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- uses: actions/checkout@v2
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- run: brew install yosys
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- run: ./flow.sh syn

‎.gitignore‎

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*.lxt
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.DS_Store
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tags
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lint.log script src
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async_fifo_syn.v
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lint.log

‎README.md‎

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# Asynchronous dual clock FIFO
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![CI](https://github.com/dpretet/async_fifo/actions/workflows/ci.yaml/badge.svg?branch=master)
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[![GitHub issues](https://img.shields.io/github/issues/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/issues)
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[![GitHub forks](https://img.shields.io/github/forks/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/network)
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[![GitHub stars](https://img.shields.io/github/stars/dpretet/async_fifo)](https://github.com/dpretet/async_fifo/stargazers)
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The simulation testcases available use [Icarus Verilog](http://iverilog.icarus.com) and [SVUT](https://github.com/dpretet/svut) tool to run the tests.
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# Documentation
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The FIFO is fully functional and used in many successful project
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# Usage
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RTL sources are present in RTL folder under three flavors:
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- `rtl/async_fifo.v`: a basic asynchronous dual-clock FIFO
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- `rtl/async_bidir_fifo.v`: two instance of the first one into a single top level for full-duplex channel
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- `rtl/async_bidir_ramif_fifo.v`: same than previous but with external RAM
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The three FIFOs have a list file to get the associated fileset.
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The testbench in `sim/` provides an example about the instance and the configuration.
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All three top levels have the same parameters:
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- `DSIZE`: the size in bits of the datapath
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- `ASIZE`: the size in bits of the internal RAM address bus. This implies the FIFO can be configured only with power of 2 depth
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- `FALLTHROUGH`: allow to reduce the inner latency and propagate faster the data through the FIFO
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* [specification](doc/specification.rst)
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* [testplan](doc/testplan.rst)
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# License
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‎async_fifo.core‎

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filesets:
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rtl:
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files:
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- src/vlog/fifomem_dp.v
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- src/vlog/sync_r2w.v
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- src/vlog/async_bidir_fifo.v
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- src/vlog/rptr_empty.v
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- src/vlog/sync_w2r.v
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- src/vlog/wptr_full.v
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- src/vlog/fifo_2mem.v
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- src/vlog/async_bidir_ramif_fifo.v
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- src/vlog/async_fifo.v
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- src/vlog/sync_ptr.v
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file_type : verilogSource

‎doc/architecture.rst‎

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‎doc/release.rst‎

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‎doc/testplan.rst‎

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1. Test the same clock frequency on both sides. Phases can be equal or not.
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2. Test slower clock on write side
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* clock can be close to read frequency, but slower
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* clock can be very regarding read frequency
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- clock can be close to read frequency, but slower
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- clock can be very regarding read frequency
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3. Test higher clock on write side
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* clock can be close to read frequency, but higher
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* clock can be very high regarding read frequency
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- clock can be close to read frequency, but higher
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- clock can be very high regarding read frequency
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Read/Write enable control assertion
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-----------------------------------
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A second focus is put on read/write enable assertion:
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1. Read enable is always enable, unless empty = 1
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* Write enable is always asserted, data are not corrupted
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* Write enable can be occasionaly asserted, data are not corrupted
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- Write enable is always asserted, data are not corrupted
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- Write enable can be occasionaly asserted, data are not corrupted
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2. Write enable is always enable, unless full = 1
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* Read enable is always asserted, data are not corrupted
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* Read enable can be occasionaly asserted, data are not corrupted
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- Read enable is always asserted, data are not corrupted
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- Read enable can be occasionaly asserted, data are not corrupted
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3. Read and Write enable can be occasionaly asserted
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* Assertion frequency (either read or write) is periodic (1/2, 1/3, 1/2, ...)
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* Assertion frequecy is (pseudo) random
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- Assertion frequency (either read or write) is periodic (1/2, 1/3, 1/2, ...)
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- Assertion frequecy is (pseudo) random
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Test coverage
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-------------
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To ensure a wide feature feature coverage is performed, both clock frequency scale and
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read/write enable assertions have to be tested together. Big range over higher frequency
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scale factor doesn't have to considered. Only few conbinations can be tested for
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To ensure a wide feature feature coverage is performed, both clock frequency scale and
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read/write enable assertions have to be tested together. Big range over higher frequency
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scale factor doesn't have to considered. Only few combinations can be tested for
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good confidence on the IP behavior.

‎flow.sh‎

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#!/usr/bin/env bash
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# -e: exit if one command fails
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# -u: treat unset variable as an error
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# -f: disable filename expansion upon seeing *, ?, ...
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# -o pipefail: causes a pipeline to fail if any command fails
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set -e -o pipefail
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# Current script path; doesn't support symlink
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FIFO_DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" >/dev/null 2>&1 && pwd )"
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# Bash color codes
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Red='\033[0;31m'
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Green='\033[0;32m'
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Yellow='\033[0;33m'
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Blue='\033[0;34m'
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# Reset
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NC='\033[0m'
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function printerror {
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echo -e "${Red}ERROR: ${1}${NC}"
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}
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function printwarning {
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echo -e "${Yellow}WARNING: ${1}${NC}"
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}
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function printinfo {
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echo -e "${Blue}INFO: ${1}${NC}"
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}
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function printsuccess {
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echo -e "${Green}SUCCESS: ${1}${NC}"
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}
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help() {
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echo -e "${Blue}"
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echo ""
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echo "NAME"
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echo ""
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echo " Async FIFO Flow"
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echo ""
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echo "SYNOPSIS"
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echo ""
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echo " ./flow.sh -h"
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echo ""
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echo " ./flow.sh help"
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echo ""
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echo " ./flow.sh syn"
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echo ""
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echo " ./flow.sh sim"
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echo ""
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echo "DESCRIPTION"
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echo ""
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echo " This flow handles the different operations available"
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echo ""
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echo " ./flow.sh help|-h"
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echo ""
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echo " Print the help menu"
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echo ""
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echo " ./flow.sh syn"
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echo ""
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echo " Launch the synthesis script relying on Yosys"
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echo ""
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echo " ./flow.sh sim"
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echo -e "${NC}"
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}
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run_sims() {
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printinfo "Start simulation"
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cd "$FIFO_DIR"/sim
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svutRun -f files.f -test async_fifo_unit_test.sv -sim icarus
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return $?
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}
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run_syn() {
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printinfo "Start synthesis"
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cd "$FIFO_DIR/syn"
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./syn_asic.sh
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return $?
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}
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run_lint() {
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set +e
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printinfo "Start lint"
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verilator --lint-only +1800-2017ext+sv \
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-Wall -Wpedantic \
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-Wno-VARHIDDEN \
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-Wno-PINCONNECTEMPTY \
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-Wno-PINMISSING \
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./rtl/async_fifo.v \
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./rtl/fifomem.v \
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./rtl/rptr_empty.v \
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./rtl/sync_r2w.v \
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./rtl/sync_w2r.v \
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./rtl/wptr_full.v \
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--top-module async_fifo 2> lint.log
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set -e
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ec=$(grep -c "%Error:" lint.log)
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if [[ $ec -gt 1 ]]; then
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printerror "Lint failed, check ./lint.log for further details"
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return 1
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else
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printsuccess "Lint ran successfully"
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return 0
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fi
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}
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check_setup() {
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source script/setup.sh
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if [[ ! $(type iverilog) ]]; then
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printerror "Icarus-Verilog is not installed"
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exit 1
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fi
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if [[ ! $(type verilator) ]]; then
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printerror "Verilator is not installed"
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exit 1
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fi
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}
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main() {
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echo ""
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printinfo "Start Aync FIFO Flow"
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# If no argument provided, preint help and exit
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if [[ $# -eq 0 ]]; then
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help
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exit 1
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fi
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# Print help
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if [[ $1 == "-h" || $1 == "help" ]]; then
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help
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exit 0
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fi
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if [[ $1 == "lint" ]]; then
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run_lint
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exit $?
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fi
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if [[ $1 == "sim" ]]; then
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check_setup
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run_sims
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exit $?
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fi
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if [[ $1 == "syn" ]]; then
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run_syn
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return $?
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fi
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}
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main "$@"

‎rtl/async_bidir_fifo.list‎

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async_bidir_fifo.v
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fifomem.v
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fifomem_dp.v
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rptr_empty.v
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sync_ptr.v
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sync_r2w.v
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sync_w2r.v
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wptr_full.v

src/vlog/async_bidir_fifo.v renamed to rtl/async_bidir_fifo.v

File renamed without changes.

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