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GlobalISel: Add GINodeEquiv for min/max
llvm-svn: 364759
1 parent fbf67d8 commit 01bb075

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‎llvm/include/llvm/Target/GlobalISel/SelectionDAGCompat.td

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Original file line numberDiff line numberDiff line change
@@ -98,6 +98,10 @@ def : GINodeEquiv<G_FSQRT, fsqrt>;
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def : GINodeEquiv<G_FFLOOR, ffloor>;
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def : GINodeEquiv<G_FRINT, frint>;
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def : GINodeEquiv<G_FNEARBYINT, fnearbyint>;
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def : GINodeEquiv<G_SMIN, smin>;
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def : GINodeEquiv<G_SMAX, smax>;
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def : GINodeEquiv<G_UMIN, umin>;
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def : GINodeEquiv<G_UMAX, umax>;
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// Broadly speaking G_LOAD is equivalent to ISD::LOAD but there are some
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// complications that tablegen must take care of. For example, Predicates such

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smax.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
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# ERR-NOT: remark:
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# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMAX %0:sgpr, %1:sgpr (in function: smax_s32_ss)
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# ERR-NOT: remark:
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---
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name: smax_s32_ss
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $sgpr1
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; GCN-LABEL: name: smax_s32_ss
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; GCN: [[SMAX:%[0-9]+]]:sgpr(s32) = G_SMAX [[COPY]], [[COPY1]]
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; GCN: S_ENDPGM 0, implicit [[SMAX]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smax_s32_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: smax_s32_sv
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smax_s32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: smax_s32_vs
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smax_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: smax_s32_vv
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_MAX_I32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MAX_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_SMAX %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-smin.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
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# ERR-NOT: remark:
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# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_SMIN %0:sgpr, %1:sgpr (in function: smin_s32_ss)
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# ERR-NOT: remark:
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---
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name: smin_s32_ss
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legalized: true
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regBankSelected: true
13+
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body: |
15+
bb.0:
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liveins: $sgpr0, $sgpr1
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; GCN-LABEL: name: smin_s32_ss
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; GCN: [[SMIN:%[0-9]+]]:sgpr(s32) = G_SMIN [[COPY]], [[COPY1]]
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; GCN: S_ENDPGM 0, implicit [[SMIN]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smin_s32_sv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: smin_s32_sv
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
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%0:sgpr(s32) = COPY $sgpr0
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%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smin_s32_vs
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: smin_s32_vs
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...
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---
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name: smin_s32_vv
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legalized: true
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regBankSelected: true
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body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: smin_s32_vv
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
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; GCN: [[V_MIN_I32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_I32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MIN_I32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:vgpr(s32) = COPY $vgpr1
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%2:vgpr(s32) = G_SMIN %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umax.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
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# RUN: FileCheck -check-prefix=ERR %s < %t
4+
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# ERR-NOT: remark:
6+
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_UMAX %0:sgpr, %1:sgpr (in function: umax_s32_ss)
7+
# ERR-NOT: remark:
8+
9+
---
10+
name: umax_s32_ss
11+
legalized: true
12+
regBankSelected: true
13+
14+
body: |
15+
bb.0:
16+
liveins: $sgpr0, $sgpr1
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; GCN-LABEL: name: umax_s32_ss
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; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; GCN: [[UMAX:%[0-9]+]]:sgpr(s32) = G_UMAX [[COPY]], [[COPY1]]
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; GCN: S_ENDPGM 0, implicit [[UMAX]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
27+
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---
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name: umax_s32_sv
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legalized: true
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regBankSelected: true
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33+
body: |
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bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: umax_s32_sv
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; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39+
; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
40+
; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
41+
%0:sgpr(s32) = COPY $sgpr0
42+
%1:vgpr(s32) = COPY $vgpr0
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%2:vgpr(s32) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
46+
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---
48+
name: umax_s32_vs
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legalized: true
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regBankSelected: true
51+
52+
body: |
53+
bb.0:
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liveins: $sgpr0, $vgpr0
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; GCN-LABEL: name: umax_s32_vs
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
58+
; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
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; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
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%0:vgpr(s32) = COPY $vgpr0
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%1:sgpr(s32) = COPY $sgpr0
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%2:vgpr(s32) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...
65+
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---
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name: umax_s32_vv
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legalized: true
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regBankSelected: true
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71+
body: |
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bb.0:
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liveins: $vgpr0, $vgpr1
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; GCN-LABEL: name: umax_s32_vv
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; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
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; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
77+
; GCN: [[V_MAX_U32_e64_:%[0-9]+]]:vgpr_32 = V_MAX_U32_e64 [[COPY]], [[COPY1]], implicit $exec
78+
; GCN: S_ENDPGM 0, implicit [[V_MAX_U32_e64_]]
79+
%0:vgpr(s32) = COPY $vgpr0
80+
%1:vgpr(s32) = COPY $vgpr1
81+
%2:vgpr(s32) = G_UMAX %0, %1
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S_ENDPGM 0, implicit %2
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...

‎llvm/test/CodeGen/AMDGPU/GlobalISel/inst-select-umin.mir

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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=gfx900 -run-pass=instruction-select -global-isel-abort=2 -pass-remarks-missed='gisel*' -verify-machineinstrs %s -o - 2>%t | FileCheck -check-prefix=GCN %s
3+
# RUN: FileCheck -check-prefix=ERR %s < %t
4+
5+
# ERR-NOT: remark:
6+
# ERR: remark: <unknown>:0:0: cannot select: %2:sgpr(s32) = G_UMIN %0:sgpr, %1:sgpr (in function: umin_s32_ss)
7+
# ERR-NOT: remark:
8+
9+
---
10+
name: umin_s32_ss
11+
legalized: true
12+
regBankSelected: true
13+
14+
body: |
15+
bb.0:
16+
liveins: $sgpr0, $sgpr1
17+
; GCN-LABEL: name: umin_s32_ss
18+
; GCN: [[COPY:%[0-9]+]]:sgpr(s32) = COPY $sgpr0
19+
; GCN: [[COPY1:%[0-9]+]]:sgpr(s32) = COPY $sgpr1
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; GCN: [[UMIN:%[0-9]+]]:sgpr(s32) = G_UMIN [[COPY]], [[COPY1]]
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; GCN: S_ENDPGM 0, implicit [[UMIN]](s32)
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%0:sgpr(s32) = COPY $sgpr0
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%1:sgpr(s32) = COPY $sgpr1
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%2:sgpr(s32) = G_UMIN %0, %1
25+
S_ENDPGM 0, implicit %2
26+
...
27+
28+
---
29+
name: umin_s32_sv
30+
legalized: true
31+
regBankSelected: true
32+
33+
body: |
34+
bb.0:
35+
liveins: $sgpr0, $vgpr0
36+
; GCN-LABEL: name: umin_s32_sv
37+
; GCN: [[COPY:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
38+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr0
39+
; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
40+
; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
41+
%0:sgpr(s32) = COPY $sgpr0
42+
%1:vgpr(s32) = COPY $vgpr0
43+
%2:vgpr(s32) = G_UMIN %0, %1
44+
S_ENDPGM 0, implicit %2
45+
...
46+
47+
---
48+
name: umin_s32_vs
49+
legalized: true
50+
regBankSelected: true
51+
52+
body: |
53+
bb.0:
54+
liveins: $sgpr0, $vgpr0
55+
; GCN-LABEL: name: umin_s32_vs
56+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
57+
; GCN: [[COPY1:%[0-9]+]]:sreg_32_xm0 = COPY $sgpr0
58+
; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
59+
; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
60+
%0:vgpr(s32) = COPY $vgpr0
61+
%1:sgpr(s32) = COPY $sgpr0
62+
%2:vgpr(s32) = G_UMIN %0, %1
63+
S_ENDPGM 0, implicit %2
64+
...
65+
66+
---
67+
name: umin_s32_vv
68+
legalized: true
69+
regBankSelected: true
70+
71+
body: |
72+
bb.0:
73+
liveins: $vgpr0, $vgpr1
74+
; GCN-LABEL: name: umin_s32_vv
75+
; GCN: [[COPY:%[0-9]+]]:vgpr_32 = COPY $vgpr0
76+
; GCN: [[COPY1:%[0-9]+]]:vgpr_32 = COPY $vgpr1
77+
; GCN: [[V_MIN_U32_e64_:%[0-9]+]]:vgpr_32 = V_MIN_U32_e64 [[COPY]], [[COPY1]], implicit $exec
78+
; GCN: S_ENDPGM 0, implicit [[V_MIN_U32_e64_]]
79+
%0:vgpr(s32) = COPY $vgpr0
80+
%1:vgpr(s32) = COPY $vgpr1
81+
%2:vgpr(s32) = G_UMIN %0, %1
82+
S_ENDPGM 0, implicit %2
83+
...

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